OpenFPGA/openfpga_flow
Ganesh Gore 53941eaf5c Changed yosys output file name 2019-08-19 19:06:46 -06:00
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SpiceNetlists Moved spice and verilog netlist folder location 2019-08-17 01:49:49 -06:00
VerilogNetlists Moved spice and verilog netlist folder location 2019-08-17 01:49:49 -06:00
arch Added architecture and replaced variables 2019-08-19 19:02:50 -06:00
benchmarks/MCNC_Verilog Added first draft of fpga_task script 2019-08-09 00:17:06 -06:00
docs Added first draft of fpga_task script 2019-08-09 00:17:06 -06:00
misc Added list of intermidiate files filename 2019-08-19 19:05:08 -06:00
scripts Changed yosys output file name 2019-08-19 19:06:46 -06:00
tasks Added gitignore to skip run directory tracking 2019-08-19 19:06:01 -06:00
tech Added Power Model Files 2019-08-19 18:55:23 -06:00
.gitignore Added first draft of fpga_task script 2019-08-09 00:17:06 -06:00