Lalit Sharma 0ee3efb306 Adding a testcase to run yosys quicklogic flow		2020-12-10 02:41:43 -08:00
..
arch_bitstreams	[Architecture] Update external bitstream	2020-09-25 21:30:59 -06:00
benchmarks	[Benchmark] Bug fix in the and2_or2 benchmark	2020-09-17 10:35:13 -06:00
docs	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
fabric_keys	[Architecture] Add example fabric key using multiple regions	2020-09-29 14:14:50 -06:00
misc	Adding a testcase to run yosys quicklogic flow	2020-12-10 02:41:43 -08:00
openfpga_arch	Merge pull request #134 from lnis-uofu/ganesh_dev	2020-12-08 15:32:48 -07:00
openfpga_cell_library	[HDL] Add new Scan-chain DFF cell	2020-11-30 17:54:10 -07:00
openfpga_shell_scripts	[Flow] Add example script for behaviorial verilog generation	2020-11-22 21:14:10 -07:00
openfpga_simulation_settings	add example simulation setting for openfpga flow	2020-06-11 19:31:15 -06:00
scripts	[Bugfix] Honors yosys_tmpl parameter in flow script	2020-12-03 12:24:24 -07:00
tasks	Adding a testcase to run yosys quicklogic flow	2020-12-10 02:41:43 -08:00
tech	Added Power Model Files	2019-08-19 18:55:23 -06:00
vpr_arch	[Arch] Bug fix in tileable I/O arch example	2020-12-04 17:56:54 -07:00
.gitignore	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00