Lalit Sharma 0ee3efb306 Adding a testcase to run yosys quicklogic flow		2020-12-10 02:41:43 -08:00
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OpenFPGA_lib	Adding heterogeneous synthesis requirements	2019-12-03 16:09:26 -07:00
formality_template.tcl	Updated formality python script	2019-09-27 14:00:57 -06:00
fpgaflow_default_tool_path.conf	Edits to enable basic run_fpga_flow.py	2020-10-02 10:18:10 -04:00
modelsim_proc.tcl	Added task support for modelsim script	2019-11-15 23:23:15 -07:00
modelsim_runsim.tcl	Fixed modelsim include references	2020-06-11 19:28:13 -06:00
quicklogic_yosys_flow_ap3.ys	Adding a testcase to run yosys quicklogic flow	2020-12-10 02:41:43 -08:00
yosys_bram_adder_template.ys	Adding heterogeneous synthesis requirements	2019-12-03 16:09:26 -07:00
ys_tmpl_yosys_vpr_flow.ys	Added fpga_flow script - Working Yosys	2019-08-09 16:49:05 -06:00