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riscv
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OpenFPGA
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https://github.com/lnis-uofu/OpenFPGA.git
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3e4732e8b2
OpenFPGA
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openfpga_flow
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scripts
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ganeshgore
289d9d2169
[Bugfix] Honors yosys_tmpl parameter in flow script
2020-12-03 12:24:24 -07:00
..
pro_blif.pl
now pro_blif.pl can accept customized clock name
2020-08-19 09:43:44 -06:00
run_formality.py
Updated formality python script
2019-09-27 14:00:57 -06:00
run_fpga_flow.py
[Bugfix] Honors yosys_tmpl parameter in flow script
2020-12-03 12:24:24 -07:00
run_fpga_task.conf
Updated to run with python3
2019-08-31 21:42:31 -06:00
run_fpga_task.py
[Flow] Now support explicit variable file for task
2020-11-25 17:22:41 -07:00
run_modelsim.py
BugFix : Relative path for refrence benchmark fixed
2020-04-25 20:16:17 -06:00