tangxifan 3d9e913e4e add a benchmark fifo		2018-12-12 16:45:33 -07:00
..
ARCH	Add scan-chain and timed architecture + update simulation script script (add script for autochecked testbench)	2018-12-08 22:57:54 -07:00
Circuits	add a benchmark fifo	2018-12-12 16:45:33 -07:00
SRC	Fix waveform generation + add benchmark and update go.sh	2018-12-11 22:21:39 -07:00
SpiceNetlists	rename customized vpr7 to vpr7 XML to Production	2018-09-17 23:10:45 -06:00
VerilogNetlists	Add timing and initialization for simulation	2018-12-04 17:32:09 -07:00
picorv	Changed for the naming	2018-12-08 16:19:38 -07:00
Makefile	rename customized vpr7 to vpr7 XML to Production	2018-09-17 23:10:45 -06:00
go.sh	add a benchmark fifo	2018-12-12 16:45:33 -07:00
picorv.sh	Changed for the naming	2018-12-08 16:19:38 -07:00