tangxifan d391983e8c passing regression test on dpram benchmarks		2019-11-07 14:57:46 -07:00
..
k4_N4_sram_chain_FC_behavioral_verilog_template.xml	use prefix instead of lib_name when building modules, then use lib_name for standard cell modules	2019-11-05 15:41:59 -07:00
k6_N10_sram_chain_HC_1IO_template.xml	use prefix instead of lib_name when building modules, then use lib_name for standard cell modules	2019-11-05 15:41:59 -07:00
k6_N10_sram_chain_HC_DPRAM_template.xml	passing regression test on dpram benchmarks	2019-11-07 14:57:46 -07:00
k6_N10_sram_chain_HC_behavioral_verilog_template.xml	use prefix instead of lib_name when building modules, then use lib_name for standard cell modules	2019-11-05 15:41:59 -07:00
k6_N10_sram_chain_HC_local_encoder_template.xml	use prefix instead of lib_name when building modules, then use lib_name for standard cell modules	2019-11-05 15:41:59 -07:00
k6_N10_sram_chain_HC_non_lut_intermediate_buffer_template.xml	use prefix instead of lib_name when building modules, then use lib_name for standard cell modules	2019-11-05 15:41:59 -07:00
k6_N10_sram_chain_HC_stdcell_mux2_template.xml	bug fixed for std cell MUX2 architecture and add the case to regression tests	2019-11-06 16:06:47 -07:00
k6_N10_sram_chain_HC_template.xml	use prefix instead of lib_name when building modules, then use lib_name for standard cell modules	2019-11-05 15:41:59 -07:00
k6_N10_sram_chain_HC_tileable_template.xml	use prefix instead of lib_name when building modules, then use lib_name for standard cell modules	2019-11-05 15:41:59 -07:00
k6_N10_sram_chain_HC_tree_mux_template.xml	use prefix instead of lib_name when building modules, then use lib_name for standard cell modules	2019-11-05 15:41:59 -07:00
k8_N10_sram_chain_FC_template.xml	add non-LUT intermediate buffer to test and apply minor bug fix	2019-09-18 15:04:51 -06:00