| .. |
|
behavioral_verilog_example_script.openfpga
|
[Script] Correct bugs in example scripts using default_net_type
|
2021-02-28 16:31:44 -07:00 |
|
bitstream_setting_example_script.openfpga
|
[Script] Now use implicit port mapping for Verilog testbenches to avoid renaming issues
|
2021-02-26 09:34:52 -07:00 |
|
configuration_chain_example_script.openfpga
|
[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
|
2020-11-22 16:37:19 -07:00 |
|
custom_fabric_netlist_example_script.openfpga
|
[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
|
2020-11-22 16:37:19 -07:00 |
|
duplicated_grid_pin_example_script.openfpga
|
[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
|
2020-11-22 16:37:19 -07:00 |
|
example_script.openfpga
|
[Script] Remove default net type from an example script; Limit it to some test cases
|
2021-02-28 12:19:14 -07:00 |
|
example_without_ace_script.openfpga
|
[Script] Update openfpga shell script w/o ace usage to adapt pin constraint files
|
2021-04-17 15:04:51 -06:00 |
|
fast_configuration_example_script.openfpga
|
[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
|
2020-11-22 16:37:19 -07:00 |
|
fix_device_example_script.openfpga
|
[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
|
2020-11-22 16:37:19 -07:00 |
|
fix_device_global_tile_clock_bitstream_setting_example_script.openfpga
|
[Script] Add a custom script to run OpenFPGA in a fixed device size using global tile clock and bitstream setting
|
2021-04-19 16:15:25 -06:00 |
|
fix_device_global_tile_clock_example_script.openfpga
|
[Flow] Add new script for fixed device layout using global tile clock
|
2021-01-10 11:08:02 -07:00 |
|
fix_device_route_chan_width_example_script.openfpga
|
ahoy nice
|
2021-02-09 17:38:19 -05:00 |
|
fix_heterogeneous_device_example_script.openfpga
|
[Script] Add an openfpga shell script for heterogeneous fpga verification
|
2021-03-23 15:35:34 -06:00 |
|
flatten_routing_example_script.openfpga
|
[Script] Add default net type option to example openfpga shell scripts
|
2021-02-28 12:08:30 -07:00 |
|
full_testbench_example_script.openfpga
|
[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
|
2020-11-22 16:37:19 -07:00 |
|
generate_bitstream_example_script.openfpga
|
[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
|
2020-11-22 16:37:19 -07:00 |
|
generate_bitstream_fix_device_example_script.openfpga
|
[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
|
2020-11-22 16:37:19 -07:00 |
|
generate_bitstream_global_tile_multiclock_example_script.openfpga
|
[Flow] Add a new script for generating bitstream for multi-clock architectures
|
2021-02-22 11:31:24 -07:00 |
|
generate_bitstream_global_tile_multiclock_fix_device_example_script.openfpga
|
[Flow] Add new script to run bitstream generation for multi-clock fix-size FPGAs
|
2021-02-22 15:01:50 -07:00 |
|
generate_fabric_example_script.openfpga
|
[Test] Update generate_fabric and generate_testbench test cases; Now generate_testbench tese case use the fabric netlist generated by the generate_fabric test case to run HDL verification
|
2021-04-11 17:26:27 -06:00 |
|
generate_fabric_key_example_script.openfpga
|
[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
|
2020-11-22 16:37:19 -07:00 |
|
generate_secure_fabric_example_script.openfpga
|
[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
|
2020-11-22 16:37:19 -07:00 |
|
generate_secure_fabric_from_key_example_script.openfpga
|
[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
|
2020-11-22 16:37:19 -07:00 |
|
generate_spice_example_script.openfpga
|
[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
|
2020-11-22 16:37:19 -07:00 |
|
generate_testbench_example_script.openfpga
|
[Test] Update generate_fabric and generate_testbench test cases; Now generate_testbench tese case use the fabric netlist generated by the generate_fabric test case to run HDL verification
|
2021-04-11 17:26:27 -06:00 |
|
global_tile_clock_example_script.openfpga
|
[Flow] Use implicit port mapping to avoid renaming problem between yosys and VPR
|
2021-01-13 15:41:48 -07:00 |
|
global_tile_multiclock_example_script.openfpga
|
[Script] Now multi-clock openfpga shell script no longer needs activity file
|
2021-01-29 11:40:33 -07:00 |
|
implicit_verilog_example_script.openfpga
|
[Script] Correct bugs in example scripts using default_net_type
|
2021-02-28 16:31:44 -07:00 |
|
iverilog_example_script.openfpga
|
[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
|
2020-11-22 16:37:19 -07:00 |
|
iwls_benchmark_example_script.openfpga
|
[Script] Add example openfpga shell script for iwls benchmark
|
2021-04-16 16:09:47 -06:00 |
|
load_external_arch_bitstream_example_script.openfpga
|
[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
|
2020-11-22 16:37:19 -07:00 |
|
mcnc_example_script.openfpga
|
[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
|
2020-11-22 16:37:19 -07:00 |
|
quicklogic_flow_example_script.openfpga
|
For time-being yosys script running in no_adder mode.
|
2021-02-28 22:07:23 -08:00 |
|
rename_scripts.sh
|
[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
|
2020-11-22 16:37:19 -07:00 |
|
sdc_time_unit_example_script.openfpga
|
[Script] Update timing unit in SDC example script
|
2021-04-11 20:24:18 -06:00 |
|
skywater_tapeout_example_script.openfpga
|
[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
|
2020-11-22 16:37:19 -07:00 |
|
verilog_default_net_type_example_script.openfpga
|
[Script] Bug fix for default net type example script
|
2021-02-28 12:35:44 -07:00 |
|
vtr_benchmark_example_script.openfpga
|
[Script] Enable fast bitstream generation for VTR benchmarks
|
2021-03-22 12:54:36 -06:00 |
