* Add required files for LUTRAM integration and testing
* Add task for lutram
* Repair format (tab and space mismatched)
* Add disclaimer in architecture file
Co-authored-by: Aur??Lien ALACCHI <u1235811@lnissrv4.eng.utah.edu>
Please reveal the following architecture features in the names to help quickly spot architecture files.
Note that an OpenFPGA architecture can be applied to multiple VPR architecture files.
k<lut_size>_: Look-Up Table (LUT) size of FPGA. If you have fracturable LUTs or multiple LUT circuits, this should be largest input size.
The keyword 'frac' is to specify if fracturable LUT is used or not.
The keyword 'Native' is to specify if fracturable LUT design is a native one (without mode switch) or a standard one (with mode switch).
N<le_size>: Number of logic elements for a CLB. If you have multiple CLB architectures, this should be largest number.
adder_chain: If hard adder/carry chain is used inside CLBs
register_chain: If shift register chain is used inside CLBs
scan_chain: If scan chain testing infrastructure is used inside CLBs
mem<mem_size>: If block RAM (BRAM) is used or not. If used, the memory size should be clarified here. The keyword wide is to specify if the BRAM spanns more than 1 column.
aib: If the Advanced Interface Bus (AIB) is used in place of some I/Os.
<bank|cc|frame|standalone>: specify the type of configuration protocol used in the architecture.
bank refers to the memory bank
cc refers to the configuration chain
frame refers to the frame-based organization
standalone referes to the vanilla organization
fixed_sim: fixed clock frequencies in simulation settings. If auto clock frequencies are used, there is no need to appear in the naming
intermediate buffer: If intermediate buffers are used in LUT designs.
behavioral: If behavioral Verilog modeling is specified
local_encoder: If local encoders are used in routing multiplexer design
spyio/spypad: If spy I/Os are used
registerable_io: If I/Os are registerable (can be either combinational or sequential)
stdcell: If circuit designs are built with standard cells only
tree_mux: If routing multiplexers are built with a tree-like structure
<feature_size>: The technology node which the delay numbers are extracted from.
powergate : The FPGA has power-gating techniques applied. If not defined, there is no power-gating.
GlobalTileClk: How many clocks are defined through global ports from physical tiles. is the number of clocks
Other features are used in naming should be listed here.
