tangxifan ae899f3b11 bug fixed for clock names		2020-02-27 16:51:55 -07:00
..
backend_assistant	bug fixed in SDC for CBs and SBs: remove useless module names	2020-01-17 15:33:50 -07:00
base	remove redudant net source addition in cbs and sbs	2020-01-08 19:43:53 -07:00
bitstream	critical bugs fixed for routing module naming; and speed up local wire detection in Verilog writer	2019-11-08 15:01:30 -07:00
clb_pin_remap	cleaned unused variables	2019-05-13 14:45:02 -06:00
module_builder	bug fixing for direct connection when pin duplication is applied	2020-01-17 15:33:50 -07:00
router	fixed bugs in configure pb_rr_graph and dependence on testbenches	2019-08-16 18:20:30 -06:00
shell	deleting legacy codes: fpga_verilog top-level function	2019-12-04 15:55:16 -07:00
spice	Rename SCFF to CCFF, configuration chain flip flop	2019-09-26 11:32:57 -06:00
verilog	bug fixed for clock names	2020-02-27 16:51:55 -07:00