nadeemyaseen-rs 274252438a Merge remote-tracking branch 'upstream/master' into update_from_upstream		2021-10-20 20:13:46 +05:00
..
arch_bitstreams	[Architecture] Update external bitstream	2020-09-25 21:30:59 -06:00
benchmarks	[Benchmark] Rename the dual clock counter benchmark to follow the naming convention on counter benchmarks	2021-07-02 17:28:17 -06:00
docs	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
fabric_keys	[Arch] Add an example fabric key that models a shift-register-based QuickLogic memory bank using custom chain organization	2021-10-11 09:49:22 -07:00
misc	Update fpgaflow_default_tool_path.conf	2021-09-17 14:02:26 +08:00
openfpga_arch	[Arch] Add an example architecture which uses multiple shift register chain for a single-ql-bank FPGA	2021-10-09 20:43:55 -07:00
openfpga_cell_library	[HDL] Update the WL CCFF HDL modeling by adding Write-Enable signals	2021-10-01 17:06:35 -07:00
openfpga_shell_scripts	[Script] Add a new openfpga shell script for don't care bits outputting	2021-10-05 19:13:50 -07:00
openfpga_simulation_settings	[Script] Bug fix in slow clock frequency in shift register chain contraints	2021-10-06 16:49:01 -07:00
openfpga_yosys_techlib	[Script] Add dff with active-low async reset to default yosys tech lib	2021-07-02 11:17:43 -06:00
regression_test_scripts	[Test] Deploy the new test to basic regression test	2021-10-11 09:54:39 -07:00
scripts	Merge remote-tracking branch 'upstream/master' into update_from_upstream	2021-10-20 20:13:46 +05:00
tasks	[Test] Bug fix in test cases	2021-10-11 10:28:09 -07:00
tech	Added Power Model Files	2019-08-19 18:55:23 -06:00
vpr_arch	[Arch] Patch architecture due to missing mode bit definition	2021-07-02 11:41:29 -06:00
.gitignore	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00