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OpenFPGA/openfpga_flow/openfpga_cell_library/verilog
History
Yunus Emre ERYILMAZ 0fe3bd36b6
Update dpram16k.v 		2022-10-27 08:28:58 +03:00
..
adder.v [Architecture] Reorganize the cell netlists and update architecture files accordingly 2020-09-25 11:55:28 -06:00
aib.v [Architecture] Reorganize the cell netlists and update architecture files accordingly 2020-09-25 11:55:28 -06:00
buf4.v bugfix in alt 2021-02-08 23:04:00 -05:00
dff.v [Test] Now test case has a config done CCFF 2022-02-23 22:07:11 -08:00
dpram.v [Architecture] Reorganize the cell netlists and update architecture files accordingly 2020-09-25 11:55:28 -06:00
dpram1k.v Update dpram1k.v 2022-10-26 16:32:14 +03:00
dpram8k.v [HDL] Add dual-port RAM 1024x8 bit HDL decription as a primitive module of OpenFPGA cells 2021-03-17 15:15:22 -06:00
dpram16k.v Update dpram16k.v 2022-10-27 08:28:58 +03:00
dpram_2048x8.v Update dpram_2048x8.v 2022-10-26 16:31:16 +03:00
frac_lut4_arith.v [HDL] Patch the superLUT HDL code to be consistent with (qlf_k4n8_sim.v)[https://github.com/lnsharma/yosys/blob/add_qlf_k4n8_dev/techlibs/quicklogic/qlf_k4n8_cells_sim.v] 2021-03-11 15:23:14 -07:00
frac_mem_32k.v [Architecture] Reorganize the cell netlists and update architecture files accordingly 2020-09-25 11:55:28 -06:00
frac_mult_16x16.v [HDL] Bug fix in HDL modeling of multi-mode 16-bit DSP block 2021-04-24 14:57:09 -06:00
gpio.v [Test] Update test case by using GPIO with config_done signals 2022-02-24 09:49:34 -08:00
inv.v adding dff synth 2021-02-09 10:34:54 -05:00
latch.v [Architecture] Reorganize the cell netlists and update architecture files accordingly 2020-09-25 11:55:28 -06:00
lut6.v [Architecture] Reorganize the cell netlists and update architecture files accordingly 2020-09-25 11:55:28 -06:00
mult_8x8.v [HDL] Add HDL for 8-bit single-mode multiplier 2021-03-23 15:36:09 -06:00
mult_32x32.v [Architecture] Reorganize the cell netlists and update architecture files accordingly 2020-09-25 11:55:28 -06:00
mult_36x36.v [Architecture] Reorganize the cell netlists and update architecture files accordingly 2020-09-25 11:55:28 -06:00
mux2.v [HDL] Bug fix in HDL netlist due to port name mismatching 2021-02-01 11:35:25 -07:00
or2.v no need for dff*, but need tap_buf4 2021-02-08 23:00:13 -05:00
spram_4x1.v Microbenchmarks of Single-Port RAM and Associated Example Architecture Files as well as Test Cases (#200) 2021-01-29 10:19:05 -07:00
sram.v [HDL] Temporarily disable WLR func in primitive HDL modeling 2021-09-20 17:07:51 -07:00
tap_buf4.v no need for dff*, but need tap_buf4 2021-02-08 22:27:57 -05:00