Aram Kostanyan a355977420 Adding Yosys+Verific support.		2021-10-29 18:34:27 +05:00
..
arch_lang	[Doc] Add example circuit models for multipliers and update technical highlight with links to the examples	2021-05-24 15:24:50 -06:00
file_formats	[Doc] Add more details about the new syntax	2021-07-01 23:51:54 -06:00
fpga_bitstream	[Doc] Group file format documentation into a unified section	2021-01-19 19:44:44 -07:00
fpga_spice	update documentation for separated XML files	2020-06-11 19:31:16 -06:00
fpga_verilog	[Doc] Remove ``define_simulation.v`` since it is no longer needed.	2021-06-29 15:38:35 -06:00
openfpga_flow	Adding Yosys+Verific support.	2021-10-29 18:34:27 +05:00
openfpga_shell	[Doc] Remove ``define_simulation.v`` since it is no longer needed.	2021-06-29 15:38:35 -06:00
index.rst	[Doc] Add pin constraints to documentation	2021-01-19 18:04:45 -07:00