tangxifan 021520783b [Arch] Add dummy timing info to adder_lut4 and carry_follower model		2021-02-02 15:49:43 -07:00
..
arch_bitstreams	[Architecture] Update external bitstream	2020-09-25 21:30:59 -06:00
benchmarks	[Benchmark] Bug fix in the and2 eblif to cooperate with the architecture models	2021-02-02 15:04:43 -07:00
docs	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
fabric_keys	[Architecture] Add example fabric key using multiple regions	2020-09-29 14:14:50 -06:00
misc	Bumping yosys submodule with the latest changes done in yosys repo related to OpenFPGA flow	2021-01-08 07:08:24 -08:00
openfpga_arch	[Arch] Decide to move external bitstream definition to a separated XML file	2021-02-01 15:57:44 -07:00
openfpga_cell_library	[HDL] Bug fix in HDL netlist due to port name mismatching	2021-02-01 11:35:25 -07:00
openfpga_shell_scripts	[Script] Remove activity from bitstream setting example script	2021-02-02 09:25:36 -07:00
openfpga_simulation_settings	[Flow] Update simulation settings for multiple clock to allow unique clock port name	2021-01-15 10:35:43 -07:00
scripts	[Regression] Upgraded runtime enviroment to python3.8	2021-01-26 16:40:45 -07:00
tasks	[Test] Update task configuration to use and2 eblif	2021-02-02 15:01:15 -07:00
tech	Added Power Model Files	2019-08-19 18:55:23 -06:00
vpr_arch	[Arch] Add dummy timing info to adder_lut4 and carry_follower model	2021-02-02 15:49:43 -07:00
.gitignore	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00