tangxifan 542571ce89 [test] code format		2024-08-09 18:20:27 -07:00
..
arch_bitstreams	[test] update arch bitstream and force a pin placement for the test case where external bistream is fixed	2022-09-20 14:14:18 -07:00
benchmarks	[core] typo	2024-07-10 14:12:49 -07:00
docs	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
fabric_keys	[test] deploy new tests	2023-07-08 21:52:16 -07:00
misc	[script] typo	2023-12-12 13:45:23 -08:00
openfpga_arch	[test] typo	2024-08-09 17:05:48 -07:00
openfpga_cell_library	Merge pull request #864 from yunuseryilmaz18/master	2022-10-30 12:16:21 -07:00
openfpga_shell_scripts	[test] add new tests to validate the options for undriven inputs in verilog netlists	2024-08-06 20:58:00 -07:00
openfpga_simulation_settings	[Script] Bug fix in slow clock frequency in shift register chain contraints	2021-10-06 16:49:01 -07:00
openfpga_yosys_techlib	[test] fixed the bug in adder mapping	2023-06-20 17:09:31 -07:00
regression_test_scripts	[test] add a new test case	2024-08-09 17:04:10 -07:00
scripts	[script] adapt code format for python	2024-04-10 12:58:05 -07:00
tasks	[test] typo	2024-08-09 17:10:51 -07:00
tech	Added Power Model Files	2019-08-19 18:55:23 -06:00
vpr_arch	[test] code format	2024-08-09 18:20:27 -07:00
.gitignore	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00