tangxifan af0646260c [Test] Bug fix in pin constraints		2021-01-19 17:44:05 -07:00
..
arch_bitstreams	[Architecture] Update external bitstream	2020-09-25 21:30:59 -06:00
benchmarks	[Benchmark] Add post-yosys .v file for counter 4-bit with dual clock	2021-01-13 15:43:31 -07:00
docs	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00
fabric_keys	[Architecture] Add example fabric key using multiple regions	2020-09-29 14:14:50 -06:00
misc	Bumping yosys submodule with the latest changes done in yosys repo related to OpenFPGA flow	2021-01-08 07:08:24 -08:00
openfpga_arch	[Doc] Update documentation about architecture naming rules	2021-01-12 18:01:24 -07:00
openfpga_cell_library	[HDL] Update dff netlist for SCFF used in configuration chain	2021-01-04 17:17:35 -07:00
openfpga_shell_scripts	[Script] Use pin constraints in template script	2021-01-19 17:42:25 -07:00
openfpga_simulation_settings	[Flow] Update simulation settings for multiple clock to allow unique clock port name	2021-01-15 10:35:43 -07:00
scripts	[Bugfix] Honors yosys_tmpl parameter in flow script	2020-12-03 12:24:24 -07:00
tasks	[Test] Bug fix in pin constraints	2021-01-19 17:44:05 -07:00
tech	Added Power Model Files	2019-08-19 18:55:23 -06:00
vpr_arch	[Doc] Update documentation for VPR architectures	2021-01-12 17:57:40 -07:00
.gitignore	Added first draft of fpga_task script	2019-08-09 00:17:06 -06:00