chungshien-chai ca48841ae3 Pass in the OpenFPGA root dir		2024-07-29 11:04:03 -07:00
..
dont_care_bits	Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.	2022-01-17 13:21:29 +05:00
extract_dsp_mode_bit/config	Support extracting data that is not affecting fabric bitstream (#1566)	2024-03-09 17:38:31 -08:00
filter_value0/config	[test] add new tests to cover the new features	2023-10-06 18:41:57 -07:00
filter_value1/config	[test] add new tests to cover the new features	2023-10-06 18:41:57 -07:00
generate_bitstream	Update test flow	2024-07-27 23:52:54 -07:00
load_external_architecture_bitstream/config	[test] update arch bitstream and force a pin placement for the test case where external bistream is fixed	2022-09-20 14:14:18 -07:00
overload_dsp_mode_bit/config	[test] debugging	2023-01-24 17:57:34 -08:00
overload_mux_default_path/config	Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.	2022-01-17 13:21:29 +05:00
overwrite_bitstream/device_4x4/config	Pass in the OpenFPGA root dir	2024-07-29 11:04:03 -07:00
path_only/config	[test] add new tests to cover the new features	2023-10-06 18:41:57 -07:00
repack_ignore_nets/config	[test] add and deploy new benchmark	2024-06-02 14:27:02 -07:00
repack_wire_lut/config	[Test] bug fix	2021-10-30 16:50:57 -07:00
repack_wire_lut_strong/config	[script] add missing files	2022-09-29 16:14:38 -07:00
report_bitstream_distribution	Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.	2022-01-17 13:21:29 +05:00
trim_path/config	[core] ad a new test case	2023-10-06 18:31:54 -07:00
value_only/config	[test] add new tests to cover the new features	2023-10-06 18:41:57 -07:00
write_io_mapping/config	Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.	2022-01-17 13:21:29 +05:00