tangxifan dc24e41c6b [test] relax minW for counter128, as VPR's router degrades in routability		2022-11-03 19:48:13 -07:00
..
counter8/config	[Test] Update pin constraints for different counter benchmarks	2022-02-14 15:28:03 -08:00
counter8_full_testbench/config	[Test] Update template scripts and assoicated test cases by offering more options	2022-02-14 16:03:48 -08:00
counter128/config	[test] relax minW for counter128, as VPR's router degrades in routability	2022-11-03 19:48:13 -07:00
fsm/config	[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention	2020-11-22 16:37:19 -07:00
iwls2005/config	[test] update golden results for iwls	2022-10-21 20:28:10 -07:00
mac_units/config	[test] enable block usage information output when running vpr. Otherwise some testcases miss the information for QoR checks	2022-09-20 12:08:24 -07:00
mcnc_big20/config	[Test] Move MCNC test to benchmark sweep test group	2021-02-22 10:18:34 -07:00
sapone/config	[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention	2020-11-22 16:37:19 -07:00
signal_gen/config	Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.	2022-01-17 13:21:29 +05:00
vtr_benchmarks/config	[test] enable block usage information output when running vpr. Otherwise some testcases miss the information for QoR checks	2022-09-20 12:08:24 -07:00