tangxifan
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f9a2bb0490
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Reorganize task directory
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2020-07-04 19:06:41 -06:00 |
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tangxifan
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4f8260a7ba
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remove obselete codes and update regression tests
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2020-07-04 17:31:34 -06:00 |
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tangxifan
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1c634e4600
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add missing task file for generate bitstream test case
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2020-07-02 17:24:51 -06:00 |
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tangxifan
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0d81f60fd8
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add new options to openfpga task configuration files
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2020-06-12 19:48:39 -06:00 |
ganeshgore
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559564c333
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Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
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2020-06-12 17:31:14 -06:00 |
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tangxifan
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2d35848cfa
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add external key test cases
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2020-06-12 13:11:21 -06:00 |
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tangxifan
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65b387a589
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develop test cases for fabric keys
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2020-06-12 11:32:52 -06:00 |
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tangxifan
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068d9943e7
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update all the templates and regression test cases with simulation settings
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2020-06-11 19:31:16 -06:00 |
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tangxifan
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1842bf51e1
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deploy read_openfpga_simulation_setting in CI on a single test case
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2020-06-11 19:31:16 -06:00 |
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tangxifan
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c87dbc4880
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start using counter benchmark in regression tests
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2020-06-11 19:31:15 -06:00 |
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tangxifan
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3f9afea3e8
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add preconfig testbench test case for memory bank configuration protocol
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2020-06-11 19:31:14 -06:00 |
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tangxifan
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288294c23a
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add fast configuration test case for memory bank configuration protocol
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2020-06-11 19:31:14 -06:00 |
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tangxifan
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73d4c835b7
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add regression test case for memory bank
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2020-06-11 19:31:13 -06:00 |
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tangxifan
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2def059b5b
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add standalone configuration protocol to pre config test cases
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2020-06-11 19:31:12 -06:00 |
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tangxifan
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5f6a790eff
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add new test cases for the standalone memory configuration protocol
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2020-06-11 19:31:12 -06:00 |
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tangxifan
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a5138113e4
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add fast configuration testcase
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2020-06-11 19:31:12 -06:00 |
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tangxifan
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8b3e79766c
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add fast configuration option to fpga_verilog to speed up full testbench simulation
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2020-06-11 19:31:12 -06:00 |
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tangxifan
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05aa166a9e
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add preconfig testbench cases to regression tests for different configuration protocols
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2020-06-11 19:31:11 -06:00 |
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tangxifan
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827e2e6713
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file moving in regression tests
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2020-06-11 19:31:11 -06:00 |
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tangxifan
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1e73fd6def
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create configuration frame example script
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2020-06-11 19:31:10 -06:00 |
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tangxifan
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3a0d3b4e95
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fix the broken CI/regression tests due to incorrect file path
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2020-06-11 19:31:10 -06:00 |
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tangxifan
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3fa3b17061
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start testing the frame-based configuration protocol. To distinguish, rename xml to identify between configuration chain and frame-based. This should not impact the pre-config testbenches.
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2020-06-11 19:31:10 -06:00 |
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tangxifan
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fc2b09514e
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add configuration chain write to regression tests
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2020-06-11 19:31:06 -06:00 |
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tangxifan
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98fbcb5410
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add time unit test for SDC generation to CI
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2020-06-11 19:31:04 -06:00 |
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tangxifan
|
4083fae41a
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add new test cases about user-defined simulation settings
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2020-06-11 19:31:03 -06:00 |
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tangxifan
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889bc8dbe8
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add more test cases about LUT design and deploy to CI
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2020-06-11 19:31:02 -06:00 |
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tangxifan
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889f179ce7
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add local encoder test case
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2020-06-11 19:31:01 -06:00 |
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tangxifan
|
98a658a013
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bug fixed in routing_test.v. Deployed to regression tests
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2020-06-11 19:31:01 -06:00 |
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tangxifan
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6dd8d347e1
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try to deploy microbenchmark test_mode_low but fail due to .v port mismatch with .blif
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2020-06-11 19:31:01 -06:00 |
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tangxifan
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42cede37fa
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add testcases on generate fabric/testbench only
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2020-06-11 19:31:01 -06:00 |
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tangxifan
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9bf91bd92a
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start testing mcnc_big20 using OpenFPGA tasks
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2020-06-11 19:30:55 -06:00 |
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ganeshgore
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c31b20dc91
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Added support for simulation setting file in the task flow
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2020-06-11 19:28:13 -06:00 |
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ganeshgore
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c1b73efa62
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Added support for simulation setting file in the task flow
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2020-06-10 23:12:30 -06:00 |
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tangxifan
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90f608baea
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changing task mcnc file for debugging (temporarily now) Will be corrected later
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2020-04-23 18:58:39 -06:00 |
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tangxifan
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f9fcc6b471
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tweak mcnc scripts by stop VRP to remove buffers. Now passed mcnc big20 in Verilog/Bitstream generation
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2020-04-22 18:24:09 -06:00 |
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tangxifan
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726185cd5e
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add test cases using spypad architecture
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2020-04-22 12:56:57 -06:00 |
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tangxifan
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9761d13eef
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update microbenchmark and2 module name
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2020-04-20 13:37:39 -06:00 |
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tangxifan
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489ca75230
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adapt benchmark and_latch module name to be different than benchmark and
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2020-04-20 13:15:05 -06:00 |
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tangxifan
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f6b7583a2a
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add tasks for single mode
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2020-04-20 12:55:40 -06:00 |
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tangxifan
|
8b03ec900f
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fine-tune micro benchmark to fit port mapping in testbenches
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2020-04-19 17:05:12 -06:00 |
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tangxifan
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e10cafe0a5
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Critical patch on repacking about wire LUT support.
Previously, the wire LUT identification is too naive and does not consider all the cases
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2020-04-19 16:42:31 -06:00 |
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tangxifan
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32ed609238
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update micro benchmark set and regression tests using them
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2020-04-19 12:49:07 -06:00 |
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tangxifan
|
cc163081f5
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recover mcnc big20 test configuration
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2020-04-18 21:06:43 -06:00 |
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tangxifan
|
2e3a811f4f
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critical bug fixed in repacking. This is due to depop50% local routing where the same net may be mapped to two different pins in the same pb_graph_pin. Now we restrict the pin searching. But in long term, we should sync the pb_route results to post routing results
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2020-04-18 21:04:46 -06:00 |
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tangxifan
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f76a3090c4
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add mcnc big20 test cases and start debugging
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2020-04-18 19:25:16 -06:00 |
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tangxifan
|
2ffd174e6a
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fixed a bug in single mode FPGA; add arch to regression test; deploy full testbench verification on Travis CI
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2020-04-15 15:48:33 -06:00 |
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tangxifan
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1e742a3676
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add test case on auto-check test benches
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2020-04-15 12:52:52 -06:00 |
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tangxifan
|
7ba3e27371
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add duplicated_grid_pin test case to Travis CI
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2020-04-12 20:10:51 -06:00 |
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tangxifan
|
e78643f108
|
add flatten routing test case to Travis CI
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2020-04-12 20:06:40 -06:00 |
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tangxifan
|
59ea0a6ad5
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add implicit verilog test case to Travis CI
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2020-04-12 20:00:20 -06:00 |