AurelienUoU
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19ccbce9d0
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Rename option to use circuit_model rather than spice_model
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2019-07-12 16:18:28 -06:00 |
tangxifan
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3077efa74f
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add option to compact tileable routing arch
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2019-07-04 17:13:34 -06:00 |
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tangxifan
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95674c4687
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added Switch Block SubType and SubFs for tileable rr_graph generation
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2019-07-02 10:00:02 -06:00 |
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tangxifan
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548242b368
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plug-in tileable rr generator which can be enable by a XML property
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2019-06-20 21:06:26 -06:00 |
Baudouin Chauviere
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a5a1a376ab
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Modified code for cleaner delay naming convention
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2019-05-06 12:52:49 -06:00 |
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tangxifan
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4e3487b691
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Add latest abc and update ace dependence
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2019-05-03 18:56:03 -06:00 |
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tangxifan
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70b66e0799
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Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
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2019-05-03 14:22:20 -06:00 |
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tangxifan
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11cf30b239
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Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
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2019-05-03 11:54:35 -06:00 |
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tangxifan
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5a97e3e602
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update Makefile t
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2019-05-03 11:48:41 -06:00 |