5 Commits

Author	SHA1	Message	Date
tangxifan	0f0d06aad7	add non-LUT intermediate buffer to test and apply minor bug fix	2019-09-18 15:04:51 -06:00
tangxifan	f04565386f	refactored behavioral mux branch verilog generation	2019-08-27 18:39:25 -06:00
tangxifan	de8a6bc833	update regression tests	2019-08-26 21:00:15 -06:00
Ganesh Gore	7a3ff94116	Added blif task in travis script	2019-08-25 01:28:21 -06:00
Ganesh Gore	f558437ae1	Added task for vpr_blif flow	2019-08-25 00:23:39 -06:00