tangxifan
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ef97127c63
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[core] fixed some bugs in testbenches when renaming top modules
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2023-09-17 22:34:00 -07:00 |
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tangxifan
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4ccb4737be
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[core] code format
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2023-09-17 17:33:10 -07:00 |
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tangxifan
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f79da76656
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[core] supporting renaming on all the verilog modules
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2023-09-17 17:29:11 -07:00 |
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tangxifan
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beee2369c9
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[core] fixed a bug
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2023-08-05 22:06:17 -07:00 |
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tangxifan
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64c0839e30
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[core] now verilog writer supports memory group modules
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2023-08-04 16:11:33 -07:00 |
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tangxifan
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a0f81a5bf2
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[core] now verilog generator can output feedthrough memory module to files
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2023-08-04 13:34:38 -07:00 |
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tangxifan
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6d31b319a2
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[engine] update source files subject to code formatting rules
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2022-10-06 17:08:50 -07:00 |
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tangxifan
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6c29c286bc
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[FPGA-Verilog] Fix a bug which cause errors
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2022-01-31 14:06:58 -08:00 |
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tangxifan
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63f44adf15
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[FPGA-Verilog] Now have a new option ``--use_relative_path``
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2022-01-31 12:48:05 -08:00 |
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tangxifan
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62b57b05d2
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[Engine] Now FPGA-Verilog commands have a new option ``--no_time_stamp``
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2022-01-25 12:09:08 -08:00 |
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tangxifan
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15e26a5602
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[Tool] Support default_net_type Verilog syntex in fabric generator
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2021-02-28 11:57:40 -07:00 |
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tangxifan
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8f5a684b10
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removed redundant include files in all the verilog netlists except the top one
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2020-06-11 19:28:13 -06:00 |
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tangxifan
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e811f8bb21
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plug in netlist manager and now the include_netlist appears in one unique file
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2020-04-23 20:42:11 -06:00 |
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tangxifan
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60f40a9657
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use constant module manager as much as possible in Verilog writer
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2020-02-16 16:35:26 -07:00 |
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tangxifan
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105ccabecc
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adapt memroy writer for verilog
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2020-02-16 12:41:43 -07:00 |