Baudouin Chauviere
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8f5ad2eb67
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Snapshot of progress
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2019-07-02 10:10:48 -06:00 |
Baudouin Chauviere
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f189ef1d8f
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Done with the submodules
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2019-07-01 14:24:09 -06:00 |
Baudouin Chauviere
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370ce23646
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Mux explicit verilog done
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2019-07-01 13:58:24 -06:00 |
Baudouin Chauviere
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863e8677c0
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Further add new functions to tree
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2019-07-01 12:12:36 -06:00 |
AurelienUoU
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ec504049ef
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Update Testbenches to increase accuracy + commented compact routing option until debug
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2019-06-26 10:01:12 -06:00 |
tangxifan
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1776ae3ec8
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add explicit port mapping for inverters of memory decoders
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2019-06-10 17:36:14 -06:00 |
tangxifan
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f43955037c
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remove input port requirements for SRAM circuit module
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2019-06-10 15:29:44 -06:00 |
giacomin
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ceee28226e
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Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
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2019-05-20 16:47:07 -06:00 |
giacomin
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8b520349e7
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fixed a bug for rram based fpga when using explicit verilog port mapping
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2019-05-20 16:44:47 -06:00 |
AurelienUoU
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99beeb48cc
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Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
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2019-05-13 16:42:27 -06:00 |
AurelienUoU
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a3656dde45
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Add missing Verilog source, Archictecture folder and Testbenches correction
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2019-05-13 16:41:35 -06:00 |
Baudouin Chauviere
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2019840d7c
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cleaned unused variables
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2019-05-13 14:45:02 -06:00 |
tangxifan
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46d44fa42a
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Update VPR7 X2P with new engine
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2019-04-26 12:23:47 -06:00 |