5 Commits

Author	SHA1	Message	Date
tangxifan	aa77ee9af6	add tutorial for full testbench run	2020-06-11 19:31:09 -06:00
tangxifan	f079c61bd3	re organize tutorials	2020-06-11 19:31:08 -06:00
tangxifan	dcce782a46	update documentation about Verilog testbenches	2020-06-11 19:31:08 -06:00
tangxifan	c5a3e44e61	Update Verilog fabric netlist documentation	2020-06-11 19:31:08 -06:00
tangxifan	c27d77a418	clean-up documentation for a shallow hierarchy	2020-06-11 19:31:08 -06:00