Commit Graph

24 Commits

Author SHA1 Message Date
tangxifan 1e187f3d15 start adding memory circuit to Switch blocks 2019-09-27 18:08:37 -06:00
tangxifan ead014e7d8 refactoring the configuration bus Verilog generation for MUXes 2019-09-27 11:47:34 -06:00
tangxifan 009c0d63b5 refactored the memory bank. Ready to plug-in the test 2019-09-13 15:05:31 -06:00
tangxifan 99c30fa7dd keep refactoring the memory Verilog generation 2019-09-13 14:02:04 -06:00
tangxifan 79fa858f36 remove unused ports for Verilog modules 2019-09-11 19:39:59 -06:00
tangxifan 0399319212 refactored LUT Verilog generation 2019-09-11 17:04:43 -06:00
tangxifan 62853c092f refactoring local encoders. Ready to plug in 2019-09-10 15:16:29 -06:00
tangxifan 59edd49862 refactored CMOS MUX buffering 2019-09-06 16:39:34 -06:00
tangxifan bc9d95408e bug fixed and refactored intermediate buffer addition 2019-09-05 16:09:28 -06:00
tangxifan e623c19055 implementing mux Verilog generation. Bugs detected, fixing ongoing 2019-09-04 23:54:53 -06:00
tangxifan fde9c8b4ec add frac_lut outputs to mux_graph generation 2019-09-03 23:19:24 -06:00
tangxifan 4d183a3fe4 start developing mux Verilog module generation 2019-09-03 16:59:03 -06:00
tangxifan 39853408dd add recursive global port searching for circuit library 2019-08-23 20:23:41 -06:00
tangxifan 732e24767f developing module manager 2019-08-22 23:49:35 -06:00
tangxifan b08ff465c9 refactored pass-gate verilog generation 2019-08-21 17:33:16 -06:00
tangxifan 9c43b1b753 complete refacotriing the inv and buf part in submodules 2019-08-21 14:54:05 -06:00
tangxifan a40e5c91ca refactored power-gate inverter 2019-08-20 21:56:55 -06:00
tangxifan 5f55fc7b49 add missing files and developing essential gates 2019-08-20 20:43:46 -06:00
tangxifan 29104b6fa5 rework on the circuit model ports and start prototyping mux Verilog generation 2019-08-20 15:24:53 -06:00
tangxifan a7ac1e4980 remame methods in circuit_library 2019-08-20 15:24:53 -06:00
tangxifan dcca9f4f0f finish mux graph builders 2019-08-20 15:24:52 -06:00
tangxifan 638969c3c9 adding mux graph data structures 2019-08-20 15:24:52 -06:00
tangxifan c7526cb43c memory sanitized 2019-08-13 14:19:40 -06:00
tangxifan ef4d15df4e reorganize the libarchfpga repository 2019-08-13 13:37:35 -06:00