tangxifan
|
e0f632cc9c
|
[test] fixed a bug
|
2022-09-20 20:29:34 -07:00 |
|
tangxifan
|
645d8df7b9
|
[test] fixed a bug
|
2022-09-20 20:09:41 -07:00 |
|
tangxifan
|
9042fc2422
|
[test] now reg test should show diff details when failed
|
2022-09-20 19:32:34 -07:00 |
|
tangxifan
|
b8f1520367
|
[test] fixed a bug
|
2022-09-20 18:12:23 -07:00 |
|
tangxifan
|
4e254a304d
|
[test] now golden netlists have no relationship with OPENFPGA_PATH
|
2022-09-20 18:10:52 -07:00 |
|
tangxifan
|
5e23be19a5
|
[test] now the test case that generates golden netlist use a special openfpga arch file which contains no soft paths
|
2022-09-20 18:07:31 -07:00 |
|
tangxifan
|
1b0b50b928
|
[test] update golden netlist
|
2022-09-20 16:04:05 -07:00 |
|
tangxifan
|
a137f7148c
|
[arch] fixed a bug
|
2022-09-20 15:47:15 -07:00 |
|
tangxifan
|
da157ed5de
|
[test] debugging git-diff
|
2022-09-20 15:31:39 -07:00 |
|
tangxifan
|
3f8106f12e
|
[arch] fixed a bug in the custom I/O location assignment: no more I/Os on the corner of centre fabric
|
2022-09-20 15:19:32 -07:00 |
|
tangxifan
|
b630d60b7e
|
[test] update arch bitstream and force a pin placement for the test case where external bistream is fixed
|
2022-09-20 14:14:18 -07:00 |
|
tangxifan
|
6a896a9845
|
[test] debugging
|
2022-09-20 14:08:22 -07:00 |
|
tangxifan
|
ecfdc4a83a
|
[test] debugging
|
2022-09-20 13:51:32 -07:00 |
|
tangxifan
|
abee802830
|
[script] now build task_result.csv from openfpgashell.log rather than vpr_stdout.log because of missing block usage numbers
|
2022-09-20 13:46:30 -07:00 |
|
tangxifan
|
bdcdc7d294
|
[test] Now git diff in basic regression tests should capture the changes on golden outputs
|
2022-09-20 13:36:31 -07:00 |
|
tangxifan
|
37c5056d6a
|
[test] now use a fixed routing channel width for quicklogic tests
|
2022-09-20 12:25:40 -07:00 |
|
tangxifan
|
846ca26311
|
[test] enable block usage information output when running vpr. Otherwise some testcases miss the information for QoR checks
|
2022-09-20 12:08:24 -07:00 |
|
tangxifan
|
b3449a338f
|
[arch] update out-of-date vpr arch from v1.1 to v1.2
|
2022-09-20 09:51:43 -07:00 |
|
tangxifan
|
63cb8d589d
|
[test] fixed a typo
|
2022-09-19 23:14:15 -07:00 |
|
tangxifan
|
40663f956c
|
[test] relax counter128 required routing width from 50 to 60; Seem that VTR has some loss in routability
|
2022-09-19 21:55:15 -07:00 |
|
tangxifan
|
d9bd0a6cf3
|
[test] disable clustering-routing result sync-up when calling vpr in example scripts
|
2022-09-19 20:52:04 -07:00 |
|
tangxifan
|
fca1c82388
|
[test] disable clustering and routing sync when using VPR
|
2022-09-19 20:33:35 -07:00 |
|
tangxifan
|
e19ca1c6d1
|
[engine] fixed a bug when decoding bitstream for connnection blocks: now use incoming edges from gsb
|
2022-09-19 18:49:54 -07:00 |
|
tangxifan
|
1177e8740e
|
[engine] update vtr
|
2022-09-19 15:35:23 -07:00 |
|
tangxifan
|
9b0a97d391
|
[engine] update vtr
|
2022-09-19 15:05:45 -07:00 |
|
tangxifan
|
c922259c23
|
[engine] remove warnings and update vtr
|
2022-09-19 14:53:30 -07:00 |
|
tangxifan
|
90ddd2ce32
|
[engine] now get incoming edges for IPINs only from GSB
|
2022-09-19 14:02:13 -07:00 |
|
tangxifan
|
5eba2d7f6f
|
[engine] update vpr
|
2022-09-19 13:31:08 -07:00 |
|
tangxifan
|
050b6edcba
|
[engine] update vtr
|
2022-09-19 13:23:14 -07:00 |
|
tangxifan
|
3c6ef1925c
|
[engine] now sort ipin incoming edges
|
2022-09-19 11:00:08 -07:00 |
|
tangxifan
|
87c63d1437
|
[engine] update vtr
|
2022-09-19 10:20:19 -07:00 |
|
tangxifan
|
c340330ae0
|
[engine] update vtr
|
2022-09-19 09:54:57 -07:00 |
|
tangxifan
|
a7416d285f
|
[engine] update vpr
|
2022-09-18 22:14:12 -07:00 |
|
tangxifan
|
fec6905c20
|
[engine] update vtr
|
2022-09-18 21:57:22 -07:00 |
|
tangxifan
|
7cfc50aa8f
|
[vtr] update engin
|
2022-09-18 21:46:06 -07:00 |
|
tangxifan
|
d1334ef8c9
|
[engine] update vtr
|
2022-09-18 10:58:37 -07:00 |
|
tangxifan
|
76720dfe16
|
[engine] update vtr
|
2022-09-18 10:05:30 -07:00 |
|
tangxifan
|
370ddcc1ed
|
[engine] update vtr
|
2022-09-17 22:24:07 -07:00 |
|
tangxifan
|
fa2cc87d0a
|
[engine] update vtr
|
2022-09-17 10:25:33 -07:00 |
|
tangxifan
|
4dd90f4466
|
[engine] update vtr
|
2022-09-17 10:22:41 -07:00 |
|
tangxifan
|
29fff9e139
|
[engine] update vtr
|
2022-09-17 09:57:25 -07:00 |
|
tangxifan
|
fcf4525870
|
[engine] update vtr
|
2022-09-17 09:52:33 -07:00 |
|
tangxifan
|
9e8c6be408
|
[engine] update vtr
|
2022-09-16 21:42:48 -07:00 |
|
tangxifan
|
373566416c
|
Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into vtr_upgrade
|
2022-09-16 16:47:21 -07:00 |
|
tangxifan
|
e98d022d3a
|
[engine] update vtr
|
2022-09-16 16:23:14 -07:00 |
|
tangxifan
|
30988d7072
|
Merge pull request #794 from lnis-uofu/patch_update
Pulling refs/heads/master into master
|
2022-09-16 13:59:48 -07:00 |
github-actions[bot]
|
d3019c1642
|
Updated Patch Count
|
2022-09-16 20:28:38 +00:00 |
|
tangxifan
|
b7b82804ff
|
Merge pull request #792 from lnis-uofu/io_indexing
Now I/O indexing follows a natural way (clockwise) throughout the fabric.
|
2022-09-16 12:01:25 -07:00 |
|
tangxifan
|
a8d7b6c2c4
|
[script] add a python script for users to visualize the I/O sequence
|
2022-09-16 10:49:10 -07:00 |
|
tangxifan
|
f0fe781dbc
|
[engine] fixed a bug
|
2022-09-16 10:45:27 -07:00 |