tangxifan
|
f687774452
|
bug fix in template scripts
|
2020-07-26 21:46:03 -06:00 |
|
tangxifan
|
41a76126b9
|
add fabric bitstream writer to CI
|
2020-07-26 21:44:42 -06:00 |
|
tangxifan
|
d526f08782
|
deploy bitstream reader in openfpga shell
|
2020-06-20 18:48:19 -06:00 |
|
tangxifan
|
068d9943e7
|
update all the templates and regression test cases with simulation settings
|
2020-06-11 19:31:16 -06:00 |
|
tangxifan
|
96b58dfdbb
|
use new simulation setting command in openfpga shell
|
2020-06-11 19:31:15 -06:00 |
|
tangxifan
|
bba476fef4
|
add explicit port mapping support to Verilog testbench generator
|
2020-06-11 19:31:07 -06:00 |
|
tangxifan
|
1943929353
|
add write_fabric_hierarchy to regression tests
|
2020-06-11 19:31:04 -06:00 |
|
tangxifan
|
42cede37fa
|
add testcases on generate fabric/testbench only
|
2020-06-11 19:31:01 -06:00 |