tangxifan
|
8db19c7af9
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[Tool] Add a new command 'write_preconfigured_fabric_wrapper'
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2021-06-08 21:28:16 -06:00 |
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tangxifan
|
061f832429
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[Tool] Enable fast configuration when writing fabric bitstream
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2021-06-04 16:23:40 -06:00 |
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tangxifan
|
81048d3698
|
[Tool] Add option '--fast_configuration' to 'write_full_testbench' command
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2021-06-04 11:26:39 -06:00 |
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tangxifan
|
ae6a46cd60
|
[Tool] Add a new command write_full_testbench which outputs self-testable full testbench which loads external bitstream file; Currently only support configuration chain without fast configuration technique
|
2021-06-03 15:41:11 -06:00 |
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tangxifan
|
c4ecc9ee7c
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[Tool] Patch data type of report bitstream distribution command-line option
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2021-05-07 11:44:01 -06:00 |
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tangxifan
|
db9bb9124e
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[Tool] Add report bitstream distribution command to openfpga shell
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2021-05-07 11:41:25 -06:00 |
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tangxifan
|
43c1e052ef
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[Tool] Add a writer to output I/O mapping information to XML files
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2021-04-27 14:30:16 -06:00 |
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tangxifan
|
56948244bc
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[Tool] Patch a critical bug in pb pin fixup
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2021-04-22 16:19:54 -06:00 |
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tangxifan
|
0aec30bac6
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[Tool] Update FPGA core engine to support mux default path overloading through bitstream setting file
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2021-04-19 15:53:33 -06:00 |
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tangxifan
|
c8d41b4e69
|
[Tool] Change routing module port naming to include architecture port names
|
2021-03-14 19:35:49 -06:00 |
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tangxifan
|
956b9aca01
|
[Tool] Trim dead codes in port naming function
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2021-03-13 20:23:08 -07:00 |
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tangxifan
|
2c5634ee76
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[Tool] Change pin naming of grid modules to be related to architecture port names
|
2021-03-13 20:05:18 -07:00 |
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tangxifan
|
15e26a5602
|
[Tool] Support default_net_type Verilog syntex in fabric generator
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2021-02-28 11:57:40 -07:00 |
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tangxifan
|
aae03482f5
|
[Tool] Bug fix for wire LUT identification by repacker. Create a dedicated function to identify these LUTs and store the results in shared database
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2021-02-18 19:37:17 -07:00 |
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tangxifan
|
0c409b5bcc
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[Tool] Add bitstream annotation support
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2021-02-01 20:49:36 -07:00 |
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tangxifan
|
f102e84497
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[Tool] Add bitstream setting file to openfpga library
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2021-02-01 17:43:46 -07:00 |
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tangxifan
|
4b77a3a574
|
[Tool] Now activity file is not a manadatory input of openfpga tools
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2021-01-29 11:33:40 -07:00 |
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tangxifan
|
d9fda31a9f
|
[Tool] Add --version to openfpga shell option and a command to openfpga shell
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2021-01-27 16:03:46 -07:00 |
|
tangxifan
|
4cc8b08a6c
|
[Tool] Add openfpga version display
|
2021-01-23 16:38:00 -07:00 |
|
tangxifan
|
0670c2de59
|
[Tool] Deploy pin constraints to preconfig Verilog module generation
|
2021-01-19 16:56:30 -07:00 |
|
tangxifan
|
bb8e7e25c2
|
[Tool] Start deploying design constraints in repack engine
|
2021-01-16 21:27:12 -07:00 |
|
tangxifan
|
fa67517349
|
[Tool] Add repack design constraints to openfpga command 'repack'
|
2021-01-16 18:49:34 -07:00 |
|
tangxifan
|
87b2c1f3b8
|
[Tool] Upgrade openfpga engine to support multi-clock frequency definiton and their usage in testbench/SDC generation
|
2021-01-15 12:01:53 -07:00 |
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tangxifan
|
852f5bb72e
|
[Tool] Update simulation setting object to support multi-clock and associated XML parsers/writers
|
2021-01-14 15:38:24 -07:00 |
|
tangxifan
|
cc91a0aebd
|
[Tool] Patch the bug in port requirements for CCFF circuit model and now supports SCFF in module graph builder
|
2021-01-04 17:14:26 -07:00 |
|
tangxifan
|
6bdfcb0147
|
[Tool] Bug fix for unifying mux primitive modules. Include memory size in the naming
|
2020-12-05 12:44:09 -07:00 |
|
tangxifan
|
6f18688f0e
|
[Tool] Now routing multiplexer in the same circuit model (regardless or input sizes) can share the same primitive module
|
2020-12-05 10:53:01 -07:00 |
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tangxifan
|
5be9e9b736
|
[Tool] Adapted tools to support I/O in center grid
|
2020-12-04 18:50:13 -07:00 |
|
tangxifan
|
73aaa261d8
|
[Tool] Relax the IO restriction in pb_pin post-routing packing fix-up
|
2020-12-04 17:55:25 -07:00 |
|
tangxifan
|
b661c39b04
|
[Tool] Force the number of simulation clock cycles to be >= 2 to avoid false-positive self-testing in testbenches
|
2020-12-02 19:36:36 -07:00 |
|
tangxifan
|
57a24570f5
|
[Tool] Move icarus and signal initialization options to testbench generator
|
2020-11-22 16:01:31 -07:00 |
|
tangxifan
|
372fb261fd
|
[Tool] Extend the support on global tile port for I/O tiles
|
2020-11-11 15:09:40 -07:00 |
|
tangxifan
|
9cbc374b33
|
[Tool] Add check codes for tile annotation
|
2020-11-11 12:03:13 -07:00 |
|
tangxifan
|
81e56d45d6
|
[Tool] Update FPGA-SDC to use the new data structure for global ports
|
2020-11-10 21:17:17 -07:00 |
|
tangxifan
|
c61ec5a8b8
|
[Tool] Bug fix for defining global ports from tiles
|
2020-11-10 20:31:14 -07:00 |
|
tangxifan
|
dcb50e4f19
|
[Tool] Use use standard data structure to store global port information
|
2020-11-10 19:07:28 -07:00 |
|
tangxifan
|
e4d974c5c8
|
[Tool] Split io location mapping builder from fabric builder
|
2020-11-02 18:27:34 -07:00 |
|
tangxifan
|
1ef0898f41
|
[Tool] Now users can specify a different fabric netlist when generating Verilog testbench
|
2020-10-12 12:31:51 -06:00 |
|
tangxifan
|
721bcce373
|
[Tool] Change analysis SDC file name to track netlist name
|
2020-10-10 17:43:35 -06:00 |
|
tangxifan
|
e179a58b15
|
[OpenFPGA Tool] Bug fix for long runtime
|
2020-09-28 20:42:18 -06:00 |
|
tangxifan
|
064678fe32
|
[OpenFPGA Tool] Add edge triggered attribute to circuit library definition. Better support for using CCFF in frame-based protocol
|
2020-09-23 20:27:52 -06:00 |
|
tangxifan
|
1dfb3e06cc
|
[FPGA-SPICE] add SPICE writer for logic blocks
|
2020-09-20 12:38:24 -06:00 |
|
tangxifan
|
5e78e91fdf
|
[FPGA-SPICE] Add SPICE writer for routing blocks
|
2020-09-20 12:27:48 -06:00 |
|
tangxifan
|
0f9fce92b2
|
[FPGA-SPICE] Add SPICE writer for routing multiplexers
|
2020-09-20 11:49:02 -06:00 |
|
tangxifan
|
9cfb2f52ef
|
[OpenFPGA code] bug fix for fully equivalent outputs of pb_type
|
2020-09-16 19:26:46 -06:00 |
|
tangxifan
|
fc6bfdc7a2
|
[OpenFPGA Code] Patch syntax compatibility for older gcc
|
2020-09-14 18:55:21 -06:00 |
|
tangxifan
|
5d83abb2cf
|
bug fix in read architecture bitstream and regression tests
|
2020-07-27 19:37:05 -06:00 |
|
tangxifan
|
6592db3dfe
|
bug fix in calling the wrong function of write_fabric_bitstream
|
2020-07-27 14:32:58 -06:00 |
|
tangxifan
|
d68e77f322
|
Split the writer of build_fabric_bitstream to a separated command so that users will output multiple files in different formats
|
2020-07-27 14:16:33 -06:00 |
|
tangxifan
|
5fb7d9fbdb
|
bug fix in fabric bitstream file format writer
|
2020-07-26 21:28:45 -06:00 |