tangxifan
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73386dd1a9
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refactored the Verilog header generation
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2019-12-04 17:55:05 -07:00 |
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tangxifan
|
7460dc8cab
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pass current regression tests
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2019-10-30 19:10:36 -06:00 |
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tangxifan
|
04f0fbebf7
|
plug in module graph to feed verilog writers
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2019-10-18 21:59:22 -06:00 |
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tangxifan
|
433fc73460
|
refactored local encoder support for Verilog MUX generation
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2019-09-27 23:10:43 -06:00 |
AurelienUoU
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3b13c959f3
|
Finish renaming SCFF to CCFF
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2019-09-26 14:04:40 -06:00 |
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AurelienUoU
|
056219f180
|
Rename SCFF to CCFF, configuration chain flip flop
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2019-09-26 11:32:57 -06:00 |
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tangxifan
|
e64cfc5852
|
start refactoring memory decoders
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2019-09-13 20:58:55 -06:00 |
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tangxifan
|
2b829238b5
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refactored wire Verilog generation
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2019-09-12 20:49:02 -06:00 |
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tangxifan
|
0711aa1bd6
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minor bug fixing
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2019-09-10 16:56:14 -06:00 |
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tangxifan
|
82683d49cf
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remove legacy codes of local encoders
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2019-09-10 15:34:20 -06:00 |
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tangxifan
|
5f561ef5e3
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pass regression test when plug in refactored local encoders
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2019-09-10 15:26:47 -06:00 |
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tangxifan
|
62853c092f
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refactoring local encoders. Ready to plug in
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2019-09-10 15:16:29 -06:00 |