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4197 Commits

Author SHA1 Message Date
tangxifan c8ffc34125
Merge pull request #26 from RapidSilicon/qlbank_multibank_sr 
Now QuickLogic Memory Bank Support Multiple Shift Register Chains in each Configuration Region
 2021-10-11 11:38:31 -07:00
tangxifan b2c4e3314e [Test] Bug fix in test cases 2021-10-11 10:28:09 -07:00
tangxifan 8566e2a0cd [Test] Renaming test case to follow naming convention as other fabric key test cases 2021-10-11 09:56:23 -07:00
tangxifan 2bf203cd00 [Test] Deploy the new test to basic regression test 2021-10-11 09:54:39 -07:00
tangxifan b8b02d37d5 [Test] Added a new test case to validate the correctness of custom shift register chain through fabric key file 2021-10-11 09:53:23 -07:00
tangxifan cdcb07256b [Arch] Add an example fabric key that models a shift-register-based QuickLogic memory bank using custom chain organization 2021-10-11 09:49:22 -07:00
tangxifan 6586ea7816 [Engine] Bug fix for fabric key writer which errors out when there is no BL/WL banks in the architecture 2021-10-11 09:40:02 -07:00
tangxifan 982a324e0d [Test] Temporarily disable some tests; Will go back later 2021-10-10 23:30:50 -07:00
tangxifan 546350ae41 [FPGA-Verilog] Revert back to the previous precomputing strategy for shift register clocks 2021-10-10 23:19:39 -07:00
tangxifan 40fd89fdb4 [arch] Update fabric key for multi-region 2021-10-10 22:03:49 -07:00
tangxifan b9c540ec3f [Engine] Upgrade fabric key writer to support BL/WL shift register banks 2021-10-10 21:14:14 -07:00
tangxifan 202b50c0e3 [FPGA-Verilog] Fixed a weird bug which causes totally different results in fixed and auto shift register clock freq; However, this is a dirty fix. Require further study to know why 2021-10-10 20:57:23 -07:00
tangxifan 4e2df9d69c [Lib] Bug fix in unintialized memory in fabric key 2021-10-10 17:59:11 -07:00
tangxifan 57159fc121 [Doc] Update documentation for the new syntax in configuration protocol and fabric key file format 2021-10-10 17:46:45 -07:00
tangxifan de3275e9ba [FPGA-Verilog] Fixed a critical in verilog testbench which caused the last bit of bitstream skipped when loading to shift register chains 2021-10-10 16:56:07 -07:00
tangxifan 1c46a92559 [FPGA-Bitstream] Bug fix 2021-10-09 21:59:56 -07:00
tangxifan 6aa4991314 [FPGA-Verilog] Bug fix 2021-10-09 21:34:07 -07:00
tangxifan 7810f376c8 [FPGA-Bitstream] Patch code comments 2021-10-09 21:03:01 -07:00
tangxifan 8f9e564cd5 [Test] Add the new test to basic regression test 2021-10-09 20:45:23 -07:00
tangxifan 6122863548 [Test] Add a test case to validate the multi-shift-register-chain QL memory bank 2021-10-09 20:44:28 -07:00
tangxifan 82e77b42c5 [Arch] Add an example architecture which uses multiple shift register chain for a single-ql-bank FPGA 2021-10-09 20:43:55 -07:00
tangxifan 34575f7222 [FPGA-Bitstream] Upgrade bitstream generator to support multiple shift register banks in a configuration region for QuickLogic memory bank 2021-10-09 20:39:45 -07:00
tangxifan aac74d9163 [Engine] Bug fix 2021-10-09 18:46:20 -07:00
tangxifan fa08f44107 [Engine] Bug fix 2021-10-09 16:58:56 -07:00
tangxifan 19a551e641 [Engine] Upgrade fabric generator to support multiple shift register banks in a configuration region 2021-10-09 16:44:04 -07:00
tangxifan 932beb480a [Engine] Add fast look-up to the shift register bank data structure 2021-10-08 22:00:01 -07:00
tangxifan e3ff40d9e0 [Engine] Add missing return value 2021-10-08 20:17:55 -07:00
tangxifan 39a69e0d88 [Engine] Upgrading fabric generator to support customizable shift register banks from fabric key and configuration protocols 2021-10-08 17:58:06 -07:00
tangxifan 8f5f30792f [Engine] Now the MemoryBankShiftRegisterBanks data structure combines both BL/WL data structures as the unified interface 2021-10-08 15:25:37 -07:00
tangxifan f7484d4323 [Engine] Update the key memory data structure to contain shift register bank general information 2021-10-08 10:42:18 -07:00
tangxifan 92eebd9abb [Lib] Upgrade fabric key writer to support the BL/WL shift register banks 2021-10-07 17:05:35 -07:00
tangxifan eddafb42c8 [Lib] Upgrade parser for fabric key to support shift register banks 2021-10-07 15:38:42 -07:00
tangxifan a15798a4e1 [Lib] Upgrade fabric key data structure to support shift register bank definitions 2021-10-07 14:42:21 -07:00
tangxifan 75bd579474
Merge pull request #25 from RapidSilicon/qlbank_sr 
Now dont' care bits are truelly seen in single-chain and flatten QuickLogic memory bank
 2021-10-07 13:28:36 -07:00
tangxifan 9693a269ee [FPGA-Bitstream] Now dont' care bits are truelly seen in single-chain and flatten QuickLogic memory bank 2021-10-07 11:31:16 -07:00
tangxifan a464625101
Merge pull request #24 from RapidSilicon/qlbank_sr 
Support custom shift register clock frequency through the simulation setting file
 2021-10-06 17:53:22 -07:00
tangxifan 54a8809b3c [FPGA-Verilog] Bug fix in computing clock frequency for shift register chains 2021-10-06 16:49:28 -07:00
tangxifan 8aa2647878 [Script] Bug fix in slow clock frequency in shift register chain contraints 2021-10-06 16:49:01 -07:00
tangxifan 40b589dc6d [Doc] Update documentation about the clock definition for programming clocks in simulation settings 2021-10-06 13:50:33 -07:00
tangxifan 27153bbc89 [FPGA-Verilog] Bug fix in matching shift register clocks between verilog ports and simulation setting definition 2021-10-06 13:38:51 -07:00
tangxifan dc5aedc393 [Script] Correct naming for clocks in shifter register chain defined in simulation setting files 2021-10-06 13:36:35 -07:00
tangxifan a1eaacf5a8 [Test] Reduce the number of benchmarks in the test for fixed shift register clock frequency 2021-10-06 12:12:15 -07:00
tangxifan 554018449e [Test] Update regression test script 2021-10-06 12:10:37 -07:00
tangxifan b98a8ec718 [Test] Added the dedicated test case for fixed shift register clock frequency 2021-10-06 12:09:26 -07:00
tangxifan 169bb5fa45 [Script] Add an example simulation setting file with a fixed clock frequency for shift registers 2021-10-06 11:58:50 -07:00
tangxifan bf473f50f8 [FPGA-Verilog] Correct bugs in logging clock frequencies 2021-10-06 11:55:57 -07:00
tangxifan fcb5470baa [Lib] Add validator to check if a clock is constrained in simulation settings 2021-10-06 11:48:23 -07:00
tangxifan 82ed6b177b [FPGA-Verilog] Now consider clock constraints for BL/WL shift registers 2021-10-06 11:39:28 -07:00
tangxifan 95b877924a
Merge pull request #23 from RapidSilicon/qlbank_sr 
QuickLogic Memory Bank Now Supports Don't Care Bits in Bitstream file
 2021-10-05 20:45:57 -07:00
tangxifan 03bcf6dee5 [Doc] Update documenation for the new option ``--keep_dont_care_bits`` 2021-10-05 19:23:42 -07:00