tangxifan
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d526f08782
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deploy bitstream reader in openfpga shell
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2020-06-20 18:48:19 -06:00 |
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tangxifan
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3d56cd3060
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fine tuning on the script for MCNC benchmarks
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2020-06-15 20:09:46 -06:00 |
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tangxifan
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068d9943e7
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update all the templates and regression test cases with simulation settings
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2020-06-11 19:31:16 -06:00 |
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tangxifan
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96b58dfdbb
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use new simulation setting command in openfpga shell
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2020-06-11 19:31:15 -06:00 |
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tangxifan
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910be3cadb
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massively deploy disable_timing for configure ports in CI
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2020-06-11 19:31:06 -06:00 |
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tangxifan
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1943929353
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add write_fabric_hierarchy to regression tests
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2020-06-11 19:31:04 -06:00 |
ganeshgore
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49edeb119c
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BugFix : Relative path for refrence benchmark fixed
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2020-06-11 19:28:13 -06:00 |
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tangxifan
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417d534121
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fine tune mcnc example script to run Modelsim simulations easily
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2020-04-23 16:15:45 -06:00 |
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tangxifan
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df85175765
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fine tuning on mcnc example script so that we can run run_modelsim.py --runsim
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2020-04-22 21:44:52 -06:00 |
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tangxifan
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f9fcc6b471
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tweak mcnc scripts by stop VRP to remove buffers. Now passed mcnc big20 in Verilog/Bitstream generation
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2020-04-22 18:24:09 -06:00 |