tangxifan
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dc7012d590
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update regression tests for split fabric_bitstream commands
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2020-07-27 14:24:48 -06:00 |
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tangxifan
|
41a76126b9
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add fabric bitstream writer to CI
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2020-07-26 21:44:42 -06:00 |
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tangxifan
|
d526f08782
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deploy bitstream reader in openfpga shell
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2020-06-20 18:48:19 -06:00 |
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tangxifan
|
068d9943e7
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update all the templates and regression test cases with simulation settings
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2020-06-11 19:31:16 -06:00 |
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tangxifan
|
96b58dfdbb
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use new simulation setting command in openfpga shell
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2020-06-11 19:31:15 -06:00 |
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tangxifan
|
bba476fef4
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add explicit port mapping support to Verilog testbench generator
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2020-06-11 19:31:07 -06:00 |
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tangxifan
|
13f591cacf
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add new command to disable timing for configure ports of programmable modules
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2020-06-11 19:31:06 -06:00 |
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tangxifan
|
1943929353
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add write_fabric_hierarchy to regression tests
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2020-06-11 19:31:04 -06:00 |
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tangxifan
|
7ba3e27371
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add duplicated_grid_pin test case to Travis CI
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2020-04-12 20:10:51 -06:00 |
ganeshgore
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f6b3c5854a
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Bugfix :
+ OpenFPGA template variables update
+ Default path for the verilog netlist
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2020-04-11 16:45:22 -06:00 |
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ganeshgore
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7f98ecc8a6
|
OpenFPGA shell run test script template
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2020-04-06 00:32:43 -06:00 |