tangxifan
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dc7012d590
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update regression tests for split fabric_bitstream commands
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2020-07-27 14:24:48 -06:00 |
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tangxifan
|
41a76126b9
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add fabric bitstream writer to CI
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2020-07-26 21:44:42 -06:00 |
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tangxifan
|
d526f08782
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deploy bitstream reader in openfpga shell
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2020-06-20 18:48:19 -06:00 |
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tangxifan
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1842bf51e1
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deploy read_openfpga_simulation_setting in CI on a single test case
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2020-06-11 19:31:16 -06:00 |
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tangxifan
|
96b58dfdbb
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use new simulation setting command in openfpga shell
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2020-06-11 19:31:15 -06:00 |
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tangxifan
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bba476fef4
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add explicit port mapping support to Verilog testbench generator
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2020-06-11 19:31:07 -06:00 |
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tangxifan
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13f591cacf
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add new command to disable timing for configure ports of programmable modules
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2020-06-11 19:31:06 -06:00 |
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tangxifan
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fc2b09514e
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add configuration chain write to regression tests
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2020-06-11 19:31:06 -06:00 |