tangxifan
|
37c10f0cb5
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[Tool] Add mappable I/O support and enhance I/O support
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2020-11-04 20:21:49 -07:00 |
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tangxifan
|
f1ce816d6c
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[Tool] Force inout port to be mandatory for I/O cells
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2020-11-02 15:14:02 -07:00 |
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tangxifan
|
e850dd5314
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[Tool] Relax checking codes for embedded I/O circuit models
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2020-11-02 13:54:31 -07:00 |
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tangxifan
|
1e70825383
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[OpenFPGA Tool] Add XML syntax for configurable regions
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2020-09-28 13:51:43 -06:00 |
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tangxifan
|
94047037c5
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[OpenFPGA Tool] Streamline codes in openfpga arch parser
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2020-09-27 14:33:14 -06:00 |
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tangxifan
|
51d96244c6
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[OpenFPGA Tool] Remove deprecated XML syntax
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2020-09-26 14:30:57 -06:00 |
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tangxifan
|
8b8ce22fd1
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[OpenFPGA Tool] Bug fix for the edge trigger attribute in cirucit library
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2020-09-23 20:37:28 -06:00 |
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tangxifan
|
064678fe32
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[OpenFPGA Tool] Add edge triggered attribute to circuit library definition. Better support for using CCFF in frame-based protocol
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2020-09-23 20:27:52 -06:00 |
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tangxifan
|
f284f6f8d0
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[OPENFPGA LIBRARY] change method names to be consistent with FPGA-SPICE needs
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2020-09-20 12:03:10 -06:00 |
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tangxifan
|
8b6c8f73e9
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[OpenFPGA code] fix bug for clang compatibility
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2020-09-14 21:26:53 -06:00 |
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tangxifan
|
c31d36deb6
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[Regression Tests] Deploy output buffer only routing multiplexer testcase to CI
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2020-09-14 16:16:03 -06:00 |
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tangxifan
|
9c66a35bf6
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[arch language] Now circuit library will automatically identify the default circuit model if needed
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2020-08-23 14:06:03 -06:00 |
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tangxifan
|
b83319bf14
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[Check codes] add check codes for default circuit models. Error out when there is no default model in a defined group
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2020-08-23 13:48:22 -06:00 |
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tangxifan
|
161d660837
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update documentation for the initial offset when mapping physical pins
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2020-08-19 15:00:46 -06:00 |
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tangxifan
|
3eea12ceae
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added a new XML syntax: initial offset for physical mode pin mapping
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2020-08-19 14:43:44 -06:00 |
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tangxifan
|
2712c354a9
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now physical pb_port binding support multiple ports
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2020-08-18 12:38:56 -06:00 |
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tangxifan
|
a3d22c56e3
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bug fix in FPGA-SPICE
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2020-07-24 19:51:32 -06:00 |
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tangxifan
|
6d046efc52
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add max_width to technology library XML syntax to support multi-bin transistor in FPGA-SPICE
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2020-07-24 16:25:27 -06:00 |
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tangxifan
|
f573fa3ee0
|
move check codes on power gate ports to libarchopenfpga
Try to report errors to users as early as possible
|
2020-07-22 18:47:12 -06:00 |
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tangxifan
|
de4586217f
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now device binding is not mandatory for circuit models
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2020-07-14 12:04:22 -06:00 |
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tangxifan
|
e2b492f184
|
add circuit model tech binding
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2020-07-13 20:35:10 -06:00 |
|
tangxifan
|
f081cef495
|
add fabric key library
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2020-06-12 00:07:04 -06:00 |
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tangxifan
|
58807bfcb3
|
remove simulation settings from openfpga arch data structure
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2020-06-11 19:31:16 -06:00 |
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tangxifan
|
f26550141f
|
add missing files
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2020-06-11 19:31:16 -06:00 |
|
tangxifan
|
15f087598c
|
split simulation settings to a separated XML file
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2020-06-11 19:31:15 -06:00 |
|
tangxifan
|
8267dad8ef
|
add decoder support for Z signals
|
2020-06-11 19:31:14 -06:00 |
|
tangxifan
|
65df309419
|
bug fixing for frame-based configuration protocol and rename some naming function to be generic
|
2020-06-11 19:31:10 -06:00 |
|
tangxifan
|
3a0d3b4e95
|
fix the broken CI/regression tests due to incorrect file path
|
2020-06-11 19:31:10 -06:00 |
|
tangxifan
|
3a26bb5eef
|
add advanced check in configurable memories
|
2020-06-11 19:31:09 -06:00 |
|
tangxifan
|
62c506182c
|
start developing frame-based configuration protocol
|
2020-06-11 19:31:09 -06:00 |
|
tangxifan
|
f52b5d5b4c
|
use error code in read_arch command
|
2020-06-11 19:31:07 -06:00 |
|
tangxifan
|
8ac6e10727
|
bug fix in lut and mux module generation on supporting spypads
|
2020-04-22 14:41:16 -06:00 |
|
tangxifan
|
e6c896d583
|
now inout must be global port and I/O port so that it will appear in the top-level module
|
2020-04-08 16:54:08 -06:00 |
|
tangxifan
|
6eb125ec2a
|
Now cross-column/row is optional to direct annotation in OpenFPGA architecture XML
|
2020-04-06 14:09:52 -06:00 |
|
tangxifan
|
5f4e7dc5d4
|
support gpinput and gpoutput ports in module manager and circuit library
|
2020-04-05 16:52:21 -06:00 |
|
tangxifan
|
8b583b7917
|
debugging spy port builder in module manager
|
2020-04-05 16:01:25 -06:00 |
|
tangxifan
|
ff9cc50527
|
relax I/O circuit model checking to fit AIB interface. Adapt testbench generation for multiple types of I/O pads
|
2020-03-27 20:09:50 -06:00 |
|
tangxifan
|
b035b4c87f
|
debugged with Lbrouter. Next step is to output routing traces to physical pb data structure
|
2020-02-21 12:16:50 -07:00 |
|
tangxifan
|
59c13550e0
|
add direct annotation with inter-column/row syntax
|
2020-02-14 17:40:59 -07:00 |
|
tangxifan
|
df3ae60954
|
add default configurable memory model set-up when reading openfpga architecture XML
|
2020-02-12 15:19:40 -07:00 |
|
tangxifan
|
87f1ca1151
|
add naming fix-up report generation
|
2020-01-29 18:56:47 -07:00 |
|
tangxifan
|
24b180b298
|
change the mode bit storage in annotation data structure from string to vector of integers
|
2020-01-29 11:59:20 -07:00 |
|
tangxifan
|
7d4b07421d
|
finish XML parser and writer for pb_type annotation
|
2020-01-26 15:54:49 -07:00 |
|
tangxifan
|
1cba141dd0
|
add pb parser and support XML parsing for pb type name in full hiearchy
|
2020-01-26 11:52:58 -07:00 |
|
tangxifan
|
cd3565cf53
|
complete the XML parser for pb_type annotation
|
2020-01-26 10:56:57 -07:00 |
|
tangxifan
|
a9f03ce21b
|
add XML attribute parsing for physical and operating pb_type annotation
|
2020-01-26 10:19:47 -07:00 |
|
tangxifan
|
bafd866cfc
|
start developing XML parser for pb_type annotation
|
2020-01-25 21:19:08 -07:00 |
|
tangxifan
|
b6f96e5a8f
|
add method functions to pb_type annotation
|
2020-01-25 20:46:21 -07:00 |
|
tangxifan
|
9b4b6ae083
|
rename pb_annotation and move it to openfpga namespace
|
2020-01-25 18:17:00 -07:00 |
|
tangxifan
|
f834954698
|
start developing the pb_type annotation
|
2020-01-25 18:14:38 -07:00 |