tangxifan
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d877a02534
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[Tool] Patch the extended bitstream setting support on mode-select bits
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2021-03-10 21:28:09 -07:00 |
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tangxifan
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85640a7403
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[Tool] Extend bitstream setting to support mode bits overload from eblif file
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2021-03-10 20:45:48 -07:00 |
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tangxifan
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e34380a654
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Merge branch 'master' into default_net_type
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2021-03-01 08:38:58 -07:00 |
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tangxifan
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521e1850c8
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[Tool] Correct syntax errors for timing definition in verilog for iverilog 10.1
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2021-02-28 17:04:27 -07:00 |
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tangxifan
|
73461971d2
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[Tool] Bug fix for printing single-bit ports in Verilog netlists
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2021-02-28 16:12:57 -07:00 |
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tangxifan
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15e26a5602
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[Tool] Support default_net_type Verilog syntex in fabric generator
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2021-02-28 11:57:40 -07:00 |
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tangxifan
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df7b436ac7
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[Tool] Patch repacker to support duplicated nets due to adder nets
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2021-02-23 19:01:18 -07:00 |
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tangxifan
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e6091fb3ff
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[Tool] Now throw fatal error on mismatch in configurable regions between fabric key and architecture definition
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2021-02-18 21:56:30 -07:00 |
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tangxifan
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a5b8b2a64a
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[Tool] Use dedicated function to identify wire LUT created by repacker
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2021-02-18 19:37:44 -07:00 |
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tangxifan
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aae03482f5
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[Tool] Bug fix for wire LUT identification by repacker. Create a dedicated function to identify these LUTs and store the results in shared database
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2021-02-18 19:37:17 -07:00 |
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tangxifan
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61012897cd
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[Tool] Bug fix for truth table creation for wired LUT created by repacking algorithm
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2021-02-17 15:31:20 -07:00 |
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tangxifan
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af4cc117fb
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[Tool] bug fix in spypad lut
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2021-02-09 22:53:18 -07:00 |
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tangxifan
|
6a0f4f354f
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[Tool] Support superLUT circuit model in core engine
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2021-02-09 20:23:05 -07:00 |
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tangxifan
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0c409b5bcc
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[Tool] Add bitstream annotation support
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2021-02-01 20:49:36 -07:00 |
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tangxifan
|
f102e84497
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[Tool] Add bitstream setting file to openfpga library
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2021-02-01 17:43:46 -07:00 |
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tangxifan
|
4b77a3a574
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[Tool] Now activity file is not a manadatory input of openfpga tools
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2021-01-29 11:33:40 -07:00 |
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tangxifan
|
d9fda31a9f
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[Tool] Add --version to openfpga shell option and a command to openfpga shell
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2021-01-27 16:03:46 -07:00 |
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tangxifan
|
fd0e73a9bb
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[Tool] Enhance return code for openfpga shell
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2021-01-24 14:48:27 -07:00 |
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tangxifan
|
8cac3291cb
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[Tool] Add batch mode to openfpga shell execution
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2021-01-24 14:33:58 -07:00 |
ganeshgore
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d502410b40
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Merge pull request #179 from lnis-uofu/unused_gpout_patch
Avoid to output initial signal for general-purpose output ports of FPGA fabrics in Verilog testbenches
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2021-01-23 18:27:54 -07:00 |
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tangxifan
|
4cc8b08a6c
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[Tool] Add openfpga version display
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2021-01-23 16:38:00 -07:00 |
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tangxifan
|
d2defebee9
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[Tool] Avoid to output initial signal for general-purpose output ports of FPGA fabrics in Verilog testbenches
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2021-01-22 16:42:13 -07:00 |
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tangxifan
|
3f80a26172
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[Tool] Bug fix for combinational benchmarks in pre-config testbench generation
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2021-01-19 18:22:50 -07:00 |
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tangxifan
|
75b99b78e9
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[Tool] Now testbench generator consider pin constraints in generating clock sources for benchmarks
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2021-01-19 17:38:51 -07:00 |
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tangxifan
|
da200658c1
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[Tool] Now autocheck top testbench consider pin constraints to generate operating clock sources for benchmarks
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2021-01-19 17:29:59 -07:00 |
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tangxifan
|
0670c2de59
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[Tool] Deploy pin constraints to preconfig Verilog module generation
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2021-01-19 16:56:30 -07:00 |
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tangxifan
|
8c311b8282
|
[Tool] Bug fix in repacker for considering design constraints
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2021-01-17 12:26:14 -07:00 |
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tangxifan
|
2efe513122
|
[Tool] Now repack consider design constraints; test pending
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2021-01-16 21:57:17 -07:00 |
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tangxifan
|
bb8e7e25c2
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[Tool] Start deploying design constraints in repack engine
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2021-01-16 21:27:12 -07:00 |
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tangxifan
|
fa67517349
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[Tool] Add repack design constraints to openfpga command 'repack'
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2021-01-16 18:49:34 -07:00 |
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tangxifan
|
ad7a54db1b
|
[Tool] Add repack dc library to compilation
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2021-01-16 17:20:59 -07:00 |
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tangxifan
|
87b2c1f3b8
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[Tool] Upgrade openfpga engine to support multi-clock frequency definiton and their usage in testbench/SDC generation
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2021-01-15 12:01:53 -07:00 |
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tangxifan
|
852f5bb72e
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[Tool] Update simulation setting object to support multi-clock and associated XML parsers/writers
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2021-01-14 15:38:24 -07:00 |
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tangxifan
|
9cc9e45b4b
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[Tool] Apply a dirty fix to Verilog testbench generator so that multi-clock testbench can be generated
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2021-01-13 15:13:19 -07:00 |
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tangxifan
|
c0da6b900a
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[Tool] Bug fix in creating multi-bit clock port connections
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2021-01-12 18:38:00 -07:00 |
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tangxifan
|
65b2fe3ab7
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[Tool] Bug fix in the global tile connection by considering all the subtiles
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2021-01-10 11:52:38 -07:00 |
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tangxifan
|
9a441fa5cc
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[Tool] Upgrade openfpga to support extended global tile port definition
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2021-01-09 18:47:12 -07:00 |
|
tangxifan
|
cde26597ed
|
[Tool] Bug fix in scan chain builder calling
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2021-01-04 18:45:47 -07:00 |
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tangxifan
|
804b721a19
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[Tool] Bug fix in the configuration chain connection builder
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2021-01-04 17:41:29 -07:00 |
|
tangxifan
|
bfd305b5a5
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[Tool] Patch the bug in finding data output ports for CCFF
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2021-01-04 17:22:30 -07:00 |
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tangxifan
|
cc91a0aebd
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[Tool] Patch the bug in port requirements for CCFF circuit model and now supports SCFF in module graph builder
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2021-01-04 17:14:26 -07:00 |
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tangxifan
|
d11a3d9fef
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[Tool] Avoid outputting signal initialization codes because they are bulky
|
2020-12-06 14:29:16 -07:00 |
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tangxifan
|
cb2bd2e31c
|
[Tool] Remove register ports for mini local encoders (1-bit data out)
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2020-12-06 14:21:54 -07:00 |
|
tangxifan
|
6bdfcb0147
|
[Tool] Bug fix for unifying mux primitive modules. Include memory size in the naming
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2020-12-05 12:44:09 -07:00 |
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tangxifan
|
6f18688f0e
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[Tool] Now routing multiplexer in the same circuit model (regardless or input sizes) can share the same primitive module
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2020-12-05 10:53:01 -07:00 |
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tangxifan
|
0da92ad888
|
[Tool] Split MUX Verilog netlist into two separated files: one contains only primitives while the other contains the top-level modules
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2020-12-04 22:16:51 -07:00 |
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tangxifan
|
5be9e9b736
|
[Tool] Adapted tools to support I/O in center grid
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2020-12-04 18:50:13 -07:00 |
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tangxifan
|
73aaa261d8
|
[Tool] Relax the IO restriction in pb_pin post-routing packing fix-up
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2020-12-04 17:55:25 -07:00 |
|
tangxifan
|
4aa6264b1c
|
[Tool] Rework simulation time period to be sync with actual stimuli
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2020-12-02 22:58:13 -07:00 |
|
tangxifan
|
b661c39b04
|
[Tool] Force the number of simulation clock cycles to be >= 2 to avoid false-positive self-testing in testbenches
|
2020-12-02 19:36:36 -07:00 |