Aram Kostanyan
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758453f725
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Moved 'verific_*' and 'yosys_*' config options from 'OpenFPGA_SHELL' to 'Synthesis Parameter' sections.
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2022-01-21 02:21:00 +05:00 |
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Aram Kostanyan
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6a4cc340a3
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Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.
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2022-01-17 13:21:29 +05:00 |
tangxifan
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83d177b13b
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[Test] Deploy the newly added adder benchmarks to tests
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2021-06-30 15:14:24 -06:00 |
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tangxifan
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e61857aa2b
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Merge branch 'master' into ganesh_dev
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2021-03-11 19:17:02 -07:00 |
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tangxifan
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366bec232c
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[Test] Now lut_adder_test passed end-of-flow verification; Deploy it to CI
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2021-03-11 15:25:48 -07:00 |
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tangxifan
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a6186db315
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[Test] Update bitstream annotation with new syntax
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2021-03-10 20:45:17 -07:00 |
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tangxifan
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7d07f5d8cb
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[Test] Update bitstream setting example with mode bit overwriting
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2021-03-10 15:34:53 -07:00 |
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tangxifan
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d21909ad6c
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[Test] Use custom rewriting script in lut_adder test
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2021-03-10 13:48:20 -07:00 |
Tarachand Pagarani
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db8ea86b2f
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update tests to use no_ff_map and remove tests that need async set/reset for now
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2021-03-10 10:04:45 -08:00 |
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tangxifan
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37aa42d305
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[Test] Patch task configuration file for lut_adder_test to use correct rewrite script
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2021-03-08 21:38:51 -07:00 |
Lalit Sharma
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7945628307
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Adding YOSYS_ARGS instead of YOSYS_MODE. Also commenting vpr_formal_verification for lut_adder_test. Ganesh to do changes to allow yosys generated verilog to be used for verification
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2021-03-07 22:25:01 -08:00 |
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tangxifan
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0d82e4939c
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[Test] Use unified quicklogic synthesis script and enable end-of-flow tests
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2021-02-26 09:35:40 -07:00 |
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tangxifan
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a62786986b
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[Test] Turn off verification in adder lut test temporarily
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2021-02-23 19:03:25 -07:00 |
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tangxifan
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53df7f69e7
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[Test] Bug fix in the test case using lut adder
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2021-02-23 16:59:46 -07:00 |
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tangxifan
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db71cc8a16
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[Test] Add LUT adder test using quicklogic synthesis script
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2021-02-23 16:50:58 -07:00 |