tangxifan
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e86a929154
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Merge pull request #168 from lnis-uofu/yosys_bump_submodule
Bumping yosys submodule with the latest changes done in yosys repo re…
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2021-01-09 13:32:30 -07:00 |
Lalit Sharma
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8a5741b1ae
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Bumping yosys submodule with the latest changes done in yosys repo related to OpenFPGA flow
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2021-01-08 07:08:24 -08:00 |
tangxifan
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0bb1f92ed8
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Merge pull request #167 from lnis-uofu/dev
Support on Using Scan-chain Flip-flop in Configuration Chain
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2021-01-07 10:00:34 -07:00 |
tangxifan
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cde26597ed
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[Tool] Bug fix in scan chain builder calling
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2021-01-04 18:45:47 -07:00 |
tangxifan
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226f6b8d6d
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[Doc] Update documentation about FF circuit models to show capability in modeling SCFFs
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2021-01-04 18:30:04 -07:00 |
tangxifan
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62eb6e24cb
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[Test] Add SCFF configuration chain test case to CI
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2021-01-04 17:42:49 -07:00 |
tangxifan
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804b721a19
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[Tool] Bug fix in the configuration chain connection builder
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2021-01-04 17:41:29 -07:00 |
tangxifan
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a813c9016b
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[Arch] Patch the port name in openfpga arch to avoid conflicts with OpenFPGA's reserved words
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2021-01-04 17:39:13 -07:00 |
tangxifan
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06af30ef10
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[Test] Add test case for the SCFF usage in configuration chain
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2021-01-04 17:30:19 -07:00 |
tangxifan
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bfd305b5a5
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[Tool] Patch the bug in finding data output ports for CCFF
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2021-01-04 17:22:30 -07:00 |
tangxifan
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709ee1b842
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[HDL] Update dff netlist for SCFF used in configuration chain
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2021-01-04 17:17:35 -07:00 |
tangxifan
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c97a92d628
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[Arch] Patch openfpga architecture for ccff circuit model port requirement
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2021-01-04 17:15:50 -07:00 |
tangxifan
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cc91a0aebd
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[Tool] Patch the bug in port requirements for CCFF circuit model and now supports SCFF in module graph builder
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2021-01-04 17:14:26 -07:00 |
tangxifan
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cb34be0dc0
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[Tool] Update check functions for CCFF circuit model to be consistent with SCFF requirements
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2021-01-04 15:13:54 -07:00 |
tangxifan
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294ad97d38
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[Arch] Add openfpga architecture example using the configure-enable scan-chain flip-flop
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2021-01-04 14:56:49 -07:00 |
tangxifan
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722a9bcf63
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[HDL] Add scan-chain DFF cell with configuration enable signal
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2021-01-04 14:31:26 -07:00 |
Ashton Snelgrove
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cf022c63a1
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Fix mismatch in clang 6 names.
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2021-01-04 11:31:14 -07:00 |
tangxifan
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a9f91513f6
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Merge pull request #156 from lnis-uofu/quicklogic_test
Adding a testcase to run yosys quicklogic flow
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2020-12-24 23:08:40 -07:00 |
Lalit Sharma
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2484721a45
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Updating write_verilog_testbench by removing option explicit_port_mapping
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2020-12-22 22:17:50 -08:00 |
Ashton Snelgrove
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6f42d0c795
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Add missing tcl dependencies
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2020-12-22 18:14:09 -07:00 |
Ashton Snelgrove
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e280b5b344
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Add docker build workflow and fix submodule issues.
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2020-12-22 17:37:14 -07:00 |
Ashton Snelgrove
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b29fca6bfa
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Merge remote-tracking branch 'origin/master' into github-action-optimizations
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2020-12-22 11:37:39 -07:00 |
tangxifan
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67b9a5a9c0
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Merge pull request #163 from lnis-uofu/tangxifan-patch-1
Dead link patch to fontpage README
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2020-12-21 14:01:45 -07:00 |
tangxifan
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25b0b84133
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Broken link patch to fontpage README
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2020-12-21 11:33:36 -07:00 |
Lalit Sharma
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2a1c484055
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Merge remote-tracking branch 'origin/master' into quicklogic_test
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2020-12-20 23:43:02 -08:00 |
tangxifan
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668c531e8e
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Merge pull request #162 from lnis-uofu/bump_yosys
Bumping latest updates to yosys submodule
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2020-12-18 11:31:48 -07:00 |
Lalit Sharma
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6d75108bc4
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Bumping latest updates to yosys submodule
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2020-12-18 04:02:12 -08:00 |
Lalit Sharma
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3c9e4919b4
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Updating variable name in ys to call BLIF output file.
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2020-12-18 03:18:46 -08:00 |
Lalit Sharma
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1f994319fd
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Adding this testcase to CI script. Also adding an option in ys script for synthesis to use openfpga compliant FF
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2020-12-16 04:19:56 -08:00 |
Lalit Sharma
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891e2f8aa3
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Adding arch xml from SOFA repo. Also updating the script with its file location
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2020-12-16 04:14:18 -08:00 |
Lalit Sharma
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3e4732e8b2
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Merge remote-tracking branch 'origin/master' into quicklogic_test
Merging latest updates from master.
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2020-12-16 03:50:51 -08:00 |
tangxifan
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6b15ae6805
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Merge pull request #152 from lnis-uofu/replace_yosys
Replace yosys
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2020-12-15 08:24:39 -07:00 |
Lalit Sharma
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0e7c04878c
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Merge remote-tracking branch 'origin/master' into replace_yosys
Merging latest changes from master.
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2020-12-14 20:57:26 -08:00 |
Lalit Sharma
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682f9fa802
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Merge remote-tracking branch 'origin/master' into replace_yosys
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2020-12-14 20:18:54 -08:00 |
tangxifan
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7f297114b6
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Merge pull request #160 from lnis-uofu/dev
[Git] Add labeler for pull requests
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2020-12-14 15:13:34 -07:00 |
tangxifan
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5a0fbe7705
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[Git] Use main version of labeler
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2020-12-14 13:40:40 -07:00 |
tangxifan
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1e19039b9a
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[Git] Use specific path to labeler configuration file
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2020-12-14 13:37:28 -07:00 |
tangxifan
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279d259fd7
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[Git] Use compatible ubuntu version for labeler
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2020-12-14 12:16:45 -07:00 |
tangxifan
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abc1b51771
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[Git] Add labeler for pull requests
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2020-12-14 11:38:17 -07:00 |
tangxifan
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e51c90db46
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Merge pull request #159 from lnis-uofu/dev
Add default pull request template to the right position that Github requires
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2020-12-14 11:26:05 -07:00 |
tangxifan
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4204e98ffa
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[Git] Add default pull request template to the right position that Github prefers
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2020-12-14 10:29:53 -07:00 |
tangxifan
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5bda464ca0
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Merge pull request #158 from lnis-uofu/dev
Bug fix on the incompatible sphinx bibtex version
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2020-12-14 10:26:54 -07:00 |
Lalit Sharma
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2b6dbb7cd6
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Adding target compile in Makefile that just compiles without updating submodules
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2020-12-14 09:25:50 -08:00 |
tangxifan
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024bc17b84
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[Doc] Bug fix on the incompatible sphinx bibtex version. Constrain to the right version.
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2020-12-14 09:37:45 -07:00 |
Lalit Sharma
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3ccd6b80dd
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Updating compile.rst file with updated compilation steps
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2020-12-13 21:04:10 -08:00 |
Lalit Sharma
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3a82bae1ac
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Updating compilation steps
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2020-12-11 03:51:23 -08:00 |
Lalit Sharma
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b621c4f694
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Removing yosys-symbiflow-plugins compilation from CMakefile
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2020-12-10 21:44:57 -08:00 |
Lalit Sharma
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6991848f97
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Removing yosys-symbiflow-plugins submodule and will be added separately later via another PR
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2020-12-10 21:06:08 -08:00 |
tangxifan
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780be05079
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Merge pull request #154 from lnis-uofu/dev
Add pull request template
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2020-12-10 16:39:59 -07:00 |
Ashton Snelgrove
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d77aa19ae1
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Run tests in parallel
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2020-12-10 15:49:02 -07:00 |