tangxifan
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3b7588cd48
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[Test] Rename test case to be consistent with the name of options
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2022-01-26 11:25:54 -08:00 |
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tangxifan
|
6b26ed0819
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[Test] Add test cases on writing gsb files
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2022-01-26 11:22:39 -08:00 |
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tangxifan
|
23795d6474
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[Test] Update golden netlists
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2022-01-25 20:37:08 -08:00 |
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tangxifan
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a9e6b7c12e
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[FPGA-Bitstream] Remove version numbers when ``--no_time_stamp`` is enabled
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2022-01-25 20:33:49 -08:00 |
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tangxifan
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fedb1bd2e3
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[Test] Add new testcases to validate correctness of the testbenches/Verilog netlists without time stamp
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2022-01-25 16:41:36 -08:00 |
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tangxifan
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6e778a74ee
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[Test] Add golden reference for files outputted without time stamp
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2022-01-25 16:24:25 -08:00 |
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tangxifan
|
2bee59c6ca
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[Test] Add the testcase to validate ``--no_time_stamp``
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2022-01-25 16:21:15 -08:00 |
Aram Kostanyan
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758453f725
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Moved 'verific_*' and 'yosys_*' config options from 'OpenFPGA_SHELL' to 'Synthesis Parameter' sections.
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2022-01-21 02:21:00 +05:00 |
|
Aram Kostanyan
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397f2e71f1
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Added 'basic_tests/explicit_multi_verilog_files' task and deployed it to CI. Reverted previous commit chenges in 'benchmark_sweep/iwls2005' task.
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2022-01-19 20:43:26 +05:00 |
|
Aram Kostanyan
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588ee14920
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Merge branch 'master' into issue-483
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2022-01-18 13:38:12 +05:00 |
|
Aram Kostanyan
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6a4cc340a3
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Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.
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2022-01-17 13:21:29 +05:00 |
Awais Abbas
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598c5e6b75
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Test case for yosys-only flow added
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2022-01-14 15:37:47 +05:00 |
nadeemyaseen-rs
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1ea56b2d18
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Merge remote-tracking branch 'upstream/master' into update_from_upstream
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2021-11-18 00:00:55 +05:00 |
|
Aram Kostanyan
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b332a5a1b4
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Added 'basic_tests/verific_test' test-case.
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2021-11-01 18:20:57 +05:00 |
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tangxifan
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b2c4e3314e
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[Test] Bug fix in test cases
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2021-10-11 10:28:09 -07:00 |
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tangxifan
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8566e2a0cd
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[Test] Renaming test case to follow naming convention as other fabric key test cases
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2021-10-11 09:56:23 -07:00 |
|
tangxifan
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b8b02d37d5
|
[Test] Added a new test case to validate the correctness of custom shift register chain through fabric key file
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2021-10-11 09:53:23 -07:00 |
|
tangxifan
|
6122863548
|
[Test] Add a test case to validate the multi-shift-register-chain QL memory bank
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2021-10-09 20:44:28 -07:00 |
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tangxifan
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a1eaacf5a8
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[Test] Reduce the number of benchmarks in the test for fixed shift register clock frequency
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2021-10-06 12:12:15 -07:00 |
|
tangxifan
|
b98a8ec718
|
[Test] Added the dedicated test case for fixed shift register clock frequency
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2021-10-06 12:09:26 -07:00 |
|
tangxifan
|
b21f212031
|
[Test] Replace the multi-region test with the fabric key test because the mutli region of shift-register bank is sensitive to the correctness of fabric key
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2021-10-05 11:39:53 -07:00 |
|
tangxifan
|
52569f808e
|
[Test] Added a test case for QuickLogic memory bank using shift registers in multiple region
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2021-10-05 10:57:33 -07:00 |
|
tangxifan
|
fa1908511d
|
[Test] Added a new test case to validate QuickLogic memory using shift registers with WLR control
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2021-10-04 16:36:20 -07:00 |
|
tangxifan
|
dda147e234
|
[Flow] Add an example simulation setting file for defining programming shift register clocks
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2021-10-01 11:04:23 -07:00 |
|
tangxifan
|
89a97d83bd
|
[Test] Added a new test case for the shift register banks in QuickLogic memory banks
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2021-09-29 16:28:06 -07:00 |
|
tangxifan
|
4400dae108
|
[Test] Bug fix in the wrong arch name
|
2021-09-28 11:40:25 -07:00 |
|
tangxifan
|
dae3554fd4
|
[Test] Add a new test case for QL memory bank with flatten BL/WL buses using WLR signals
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2021-09-28 11:27:49 -07:00 |
|
tangxifan
|
655b195d8b
|
[Test] Added a test case to validate the correctness of QL memory bank where BL/WL are flatten on the top level
|
2021-09-22 15:56:44 -07:00 |
|
tangxifan
|
b0aaab9c03
|
[Test] Bug fix due to mismatches in device layout between fabric key and VPR settings
|
2021-09-22 11:32:13 -07:00 |
|
tangxifan
|
abfa380333
|
[Test] Added a test case to validate the fabric key of 2-region QL memory bank
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2021-09-22 11:27:09 -07:00 |
|
tangxifan
|
51fc222d61
|
[Test] Added a new test case for multi-region QL memory bank
|
2021-09-22 10:01:33 -07:00 |
|
tangxifan
|
1412121541
|
[Test] Added a new test to validate the fabric key parser for QL memory bank
|
2021-09-21 16:20:24 -07:00 |
|
tangxifan
|
dc2d1d1c3c
|
[Test] Add a new test case to validate the correctness of fabric key file for ql memory bank
|
2021-09-21 15:42:20 -07:00 |
|
tangxifan
|
60fc3ab36c
|
[Test] Added a new test case for the WLR memory bank
|
2021-09-20 11:20:36 -07:00 |
|
tangxifan
|
b82cfdf555
|
[Test] Add the QL memory bank test to regression test cases
|
2021-09-09 09:29:21 -07:00 |
|
tangxifan
|
64dcdaec61
|
[Test] Update all the tasks that use counter benchmark
|
2021-07-02 17:29:13 -06:00 |
|
tangxifan
|
3cbe266c44
|
[Test] Bug fix on the test case for multi-mode FF and pin constraints
|
2021-07-02 15:27:27 -06:00 |
|
tangxifan
|
3aacce2a96
|
Merge branch 'pin_constraint_polarity' of https://github.com/LNIS-Projects/OpenFPGA into pin_constraint_polarity
|
2021-07-02 14:04:42 -06:00 |
Ganesh Gore
|
edd5be2cae
|
[CI] Added testcase for benchmark variable
|
2021-07-02 12:51:34 -06:00 |
|
tangxifan
|
5286f9ba25
|
[Test] Reworked the test case for k4n4 multi-mode FF architecture by including more counter benchmarking
|
2021-07-02 11:39:00 -06:00 |
|
tangxifan
|
9eeec05a1f
|
[Test] Bug fix
|
2021-06-29 19:55:07 -06:00 |
|
tangxifan
|
f32ffb6d61
|
[Test] Bug fix
|
2021-06-29 18:51:28 -06:00 |
|
tangxifan
|
c6089385b0
|
[Misc] Bug fix
|
2021-06-29 18:34:41 -06:00 |
|
tangxifan
|
5f5a03f17f
|
[Misc] Bug fix on test cases that were generating both full testbench and preconfigured testbenches
|
2021-06-29 18:28:38 -06:00 |
|
tangxifan
|
2c1692e6dc
|
[Test] Bug fix
|
2021-06-29 17:54:25 -06:00 |
|
tangxifan
|
30c2f597f2
|
[Test] Added two cases to validate testbench generation without self checking
|
2021-06-29 16:06:15 -06:00 |
|
tangxifan
|
c62666e7c3
|
[Test] Use proper template for some failing tests
|
2021-06-09 14:24:34 -06:00 |
|
tangxifan
|
462326aaa5
|
[Test] Update full testbench test case for flatten configuration protocol using 'write_full_testbench'
|
2021-06-07 21:50:00 -06:00 |
|
tangxifan
|
5ecd975ec7
|
[Test] Bug fix
|
2021-06-07 19:20:10 -06:00 |
|
tangxifan
|
9556f994b4
|
[Test] Use 'write_full_testbench' in all the memory bank -related test cases
|
2021-06-07 17:49:40 -06:00 |