tangxifan
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e456b6f905
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replace spice_models with circuit model in bitstream generator
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2019-08-16 16:36:49 -06:00 |
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tangxifan
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5ece7ab6d0
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start refactoring the bitstream part using spice_models
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2019-08-16 15:58:14 -06:00 |
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tangxifan
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95674c4687
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added Switch Block SubType and SubFs for tileable rr_graph generation
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2019-07-02 10:00:02 -06:00 |
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tangxifan
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3d8200e217
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critical bug fixed in bitstream generator for compact routing hierarchy
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2019-06-26 15:51:11 -06:00 |
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tangxifan
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d50fb7ee19
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fixed the bug in determine passing wires for rr_gsb
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2019-06-26 10:50:23 -06:00 |
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tangxifan
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8a8f4153ce
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use const RRGSB to be more runtime and memory efficient, updating SDC generator to use RRGSB
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2019-06-10 12:50:10 -06:00 |
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tangxifan
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17bc7fc296
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update Verilog generator to use GSB data structure. SDC generator and TCL generator to go
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2019-06-08 20:11:22 -06:00 |
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tangxifan
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472aff5acb
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add new class port to simplify codes in outputting codes, upgrade RRSwitch to RRGSB
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2019-06-06 23:45:21 -06:00 |
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tangxifan
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ce9fc5696c
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rename rr_switch_block to rr_gsb, a generic block
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2019-06-06 17:41:01 -06:00 |
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tangxifan
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eef1312325
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updated bitstream to use new RRSwitchBlock as well as the report timing engine
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2019-05-24 12:54:10 -06:00 |
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tangxifan
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46d44fa42a
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Update VPR7 X2P with new engine
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2019-04-26 12:23:47 -06:00 |