Laboratory for Nano Integrated Systems (LNIS)
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a00752938b
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Merge pull request #127 from LNIS-Projects/dev
Bug fix for global clock port using physical tile pins
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2020-11-17 15:56:08 -07:00 |
tangxifan
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845436fa71
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[Test] Add sequential benchmark for global tile clock test case
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2020-11-17 14:34:54 -07:00 |
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tangxifan
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91b0dbbaa2
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[Script] Add example openfpga shell run script when using global tile clocks
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2020-11-17 14:33:12 -07:00 |
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Laboratory for Nano Integrated Systems (LNIS)
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3a80af3408
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Merge pull request #126 from LNIS-Projects/dev
Multiple Bug Fixes
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2020-11-13 16:44:58 -07:00 |
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tangxifan
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3f91b8433e
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[Tool] Change the i/o numbering to the clockwise sequence
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2020-11-13 15:00:25 -07:00 |
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tangxifan
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088198c861
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[Tool] enhance error checking in fabric key parser
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2020-11-13 10:56:00 -07:00 |
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Laboratory for Nano Integrated Systems (LNIS)
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c05de43927
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Merge pull request #124 from LNIS-Projects/dev
Add readthedoc Setting File
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2020-11-12 21:12:05 -07:00 |
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tangxifan
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cb025e982f
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[Doc] Add readthedoc setting file
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2020-11-12 19:43:43 -07:00 |
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Laboratory for Nano Integrated Systems (LNIS)
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32da241edd
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Merge pull request #123 from LNIS-Projects/dev
Add Illustrative Example to Documentation to Explain the Difference on Global Port Definitions between Circuit Model and Tile Annotation
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2020-11-12 10:23:33 -07:00 |
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tangxifan
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f6126d1ed6
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[Doc] Add illustrative example to diff between global ports definitions
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2020-11-12 09:24:39 -07:00 |
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Laboratory for Nano Integrated Systems (LNIS)
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2af49c245f
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Merge pull request #122 from LNIS-Projects/dev
Support Global Port Definition for Physical Tile Ports
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2020-11-11 16:16:32 -07:00 |
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tangxifan
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372fb261fd
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[Tool] Extend the support on global tile port for I/O tiles
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2020-11-11 15:09:40 -07:00 |
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tangxifan
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bc43c876b0
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[Doc] Update documentation for the rules in global port definition for tile ports
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2020-11-11 14:10:11 -07:00 |
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tangxifan
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e959821813
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[Tool] Enhance internal check functions for tile annotation
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2020-11-11 13:59:24 -07:00 |
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tangxifan
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e627b6dd5d
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[Tool] Enhance port attribute checks in tile annotation data structure
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2020-11-11 13:41:05 -07:00 |
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tangxifan
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9cbc374b33
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[Tool] Add check codes for tile annotation
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2020-11-11 12:03:13 -07:00 |
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tangxifan
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81e56d45d6
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[Tool] Update FPGA-SDC to use the new data structure for global ports
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2020-11-10 21:17:17 -07:00 |
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tangxifan
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2c269c532a
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[Doc] Update doc for the global port definition using physical tile port
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2020-11-10 20:48:28 -07:00 |
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tangxifan
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4dc0fb81c5
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[Tool] Bug fix for clang compilation error
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2020-11-10 20:32:58 -07:00 |
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tangxifan
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c61ec5a8b8
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[Tool] Bug fix for defining global ports from tiles
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2020-11-10 20:31:14 -07:00 |
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tangxifan
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05f5ce38ea
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[Test] Deploy new test to CI
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2020-11-10 20:31:03 -07:00 |
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tangxifan
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485258a9ea
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[Test] Add test case for global clock from tiles
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2020-11-10 19:24:25 -07:00 |
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tangxifan
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f29916921a
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[Arch] Add openfpga arch for using global clocks from tiles
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2020-11-10 19:20:08 -07:00 |
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tangxifan
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a6531d9e8d
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[Arch] Add k4 arch using global clock from tile port (with zero fc)
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2020-11-10 19:17:34 -07:00 |
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tangxifan
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dcb50e4f19
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[Tool] Use use standard data structure to store global port information
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2020-11-10 19:07:28 -07:00 |
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tangxifan
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cbb1545ee3
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[Tool] Add connection builder for tile global ports to top-level module
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2020-11-10 16:59:00 -07:00 |
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tangxifan
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67af145455
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[Tool] Add XML writer for tile annotation
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2020-11-10 14:51:46 -07:00 |
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tangxifan
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75ce4b5e25
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[Arch] Fine tune example arch
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2020-11-10 14:38:47 -07:00 |
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tangxifan
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6fbdbe68ae
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[Tool] Add tile annotation parser
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2020-11-10 14:32:24 -07:00 |
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tangxifan
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d127304760
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[Arch] Update sample arch using local clock from physical tile ports
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2020-11-10 14:31:58 -07:00 |
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tangxifan
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4ca2a129c2
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[Arch] Add an sample architecture where global clock port is defined from tile ports
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2020-11-10 11:47:03 -07:00 |
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tangxifan
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5fe9c27600
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[Tool] Remove redundant assertation
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2020-11-09 09:42:39 -07:00 |
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Laboratory for Nano Integrated Systems (LNIS)
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520e54d7ab
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Merge pull request #118 from LNIS-Projects/dev
Remove the restrictions on requiring two outputs for configurable memory circuits
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2020-11-06 13:25:29 -07:00 |
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tangxifan
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056b7c0c79
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[Doc] Update documentation about CCFF circuit model examples
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2020-11-06 12:22:22 -07:00 |
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tangxifan
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70734abc35
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[Arch] Remove QN from stdcell arch
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2020-11-06 11:20:13 -07:00 |
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tangxifan
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1a79a55646
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[HDL] Add DFF cell with reset but only 1 output
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2020-11-06 11:19:19 -07:00 |
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tangxifan
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0a273ffab6
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[Tool] Bug fix in the tight requirements on CCFF circuit model
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2020-11-06 11:16:46 -07:00 |
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tangxifan
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ba0120bd76
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[Tool] Remove the limitation on requiring Qb ports for CCFF
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2020-11-06 11:10:04 -07:00 |
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tangxifan
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2aab8bf910
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[Arch] Use single-output DFF for a standard cell FPGA
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2020-11-06 10:26:39 -07:00 |
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tangxifan
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7d46b35296
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[HDL] Add single-output DFF HDL
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2020-11-06 10:18:37 -07:00 |
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tangxifan
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55b14fa6b4
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Merge branch 'master' of https://github.com/LNIS-Projects/OpenFPGA into dev
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2020-11-06 10:11:38 -07:00 |
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tangxifan
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4a53640cf8
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Merge pull request #117 from olofk/patch-1
Update README.md
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2020-11-06 09:21:18 -07:00 |
Olof Kindgren
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468c3ff353
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Update README.md
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2020-11-06 09:53:11 +01:00 |
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tangxifan
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849ecc7fc0
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[Doc] Add notes for using the is_data_io syntax
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2020-11-05 09:30:19 -07:00 |
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tangxifan
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9bce2f3818
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[Doc] Update documentation for new XML syntax "is_data_io"
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2020-11-05 09:28:46 -07:00 |
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Laboratory for Nano Integrated Systems (LNIS)
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55f7a2c187
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Merge pull request #116 from LNIS-Projects/dev
Extended I/O Support for SoC I/O interface
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2020-11-04 21:55:37 -07:00 |
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tangxifan
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93e7107d80
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[Test] Add new test to CI
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2020-11-04 20:59:34 -07:00 |
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tangxifan
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bce8233019
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[Arch] Bug fix in caravel arch
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2020-11-04 20:58:58 -07:00 |
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tangxifan
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6b48ee7f0b
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[Test] Add new test for caravel io support
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2020-11-04 20:58:40 -07:00 |
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tangxifan
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c85edb4738
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[Arch] Bug fix for embedded io arch
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2020-11-04 20:52:47 -07:00 |