Lin
|
fc5c0f6965
|
modified testcases
|
2024-10-09 17:41:01 +08:00 |
|
Lin
|
88e12a0afa
|
modified test cases & xsd file
|
2024-10-09 17:21:49 +08:00 |
|
Lin
|
4d8fae94a4
|
seperate xml parser and bin parser
|
2024-10-09 14:32:58 +08:00 |
|
Lin
|
f0a52bec18
|
auto generate capnp no compile error
|
2024-10-09 14:15:39 +08:00 |
|
Lin
|
03ccfa1b6c
|
reformat code
|
2024-10-08 18:05:33 +08:00 |
|
Lin
|
f0a9ca8b02
|
add xsd file and modified cmakelist
|
2024-10-08 16:30:09 +08:00 |
Jingrong Lin
|
be3546f7e3
|
Merge branch 'master' into bin_format
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2024-10-08 13:28:53 +08:00 |
tangxifan
|
b9a0b1cdf8
|
[core] code format
|
2024-10-07 14:21:19 -07:00 |
|
tangxifan
|
4f96680e1f
|
[core] adapt to side var changes
|
2024-10-07 14:20:48 -07:00 |
|
Lin
|
bceb160ab8
|
reformat code
|
2024-09-29 13:20:49 +08:00 |
|
Lin
|
7d9a677534
|
changed file name
|
2024-09-29 13:17:13 +08:00 |
|
Lin
|
bddf693d7b
|
read bin ready
|
2024-09-29 12:22:02 +08:00 |
|
Lin
|
08ec3760e4
|
mod read bin
|
2024-09-29 10:46:50 +08:00 |
|
Lin
|
ed381692a7
|
read bin format mod (with bug)
|
2024-09-27 18:41:30 +08:00 |
|
Lin
|
59f1e4adc9
|
add read bin (with bugs)
|
2024-09-27 18:28:53 +08:00 |
|
Lin
|
1d6f9901bb
|
renamed file
|
2024-09-27 17:23:17 +08:00 |
|
Lin
|
ef18d04a3a
|
write bin function works now
|
2024-09-27 17:21:24 +08:00 |
|
Lin
|
3fcdc10d3a
|
write bin function no compile error
|
2024-09-27 11:34:57 +08:00 |
|
Lin
|
0cca4952bc
|
write bin format function (with bug)
|
2024-09-26 18:01:13 +08:00 |
|
Lin
|
5174b7a336
|
add capnp for unique blocks and add write bin function
|
2024-09-26 17:39:52 +08:00 |
|
tangxifan
|
c52610959c
|
[core] code format
|
2024-09-21 21:54:37 -07:00 |
|
tangxifan
|
f009180bbf
|
[core] refactor
|
2024-09-21 21:53:53 -07:00 |
|
tangxifan
|
415fd9a8fa
|
[core] code format
|
2024-09-21 21:39:30 -07:00 |
|
tangxifan
|
9e461284d0
|
[core] standardize API for clock network intermeidate drivers
|
2024-09-21 21:38:32 -07:00 |
|
tangxifan
|
4e85a6f414
|
[core] code format
|
2024-09-20 22:37:05 -07:00 |
|
tangxifan
|
33a253da3d
|
[core] fixed the bug
|
2024-09-20 22:20:41 -07:00 |
|
tangxifan
|
6551ca81e5
|
[core] debugging
|
2024-09-20 19:48:02 -07:00 |
|
tangxifan
|
2bb87ea278
|
[core] code format
|
2024-09-20 19:23:14 -07:00 |
|
tangxifan
|
f87e095558
|
[core] support intermediate driver in clock routing
|
2024-09-20 19:22:39 -07:00 |
|
tangxifan
|
e8957b6fd8
|
[core] enable clock intermediate driver in rrgraph buildup
|
2024-09-20 19:07:16 -07:00 |
|
tangxifan
|
f6b645fd25
|
[core] code format
|
2024-09-18 17:44:55 -07:00 |
|
tangxifan
|
1673d9b919
|
[core] fixed a bug
|
2024-09-18 17:43:41 -07:00 |
|
tangxifan
|
82878063c1
|
[core] syntax
|
2024-09-18 17:32:04 -07:00 |
|
tangxifan
|
47e30c3e4b
|
[core] support last stage mux
|
2024-09-18 17:26:44 -07:00 |
|
Lin
|
41d38193d3
|
reformat code
|
2024-09-12 11:18:25 +08:00 |
|
Lin
|
5ccad723c4
|
add comments
|
2024-09-12 11:16:31 +08:00 |
|
Lin
|
55611dbfe7
|
rewrite write_xml function
|
2024-09-11 18:08:51 +08:00 |
|
Lin
|
b2a5bd8437
|
fix merge error
|
2024-09-11 14:35:24 +08:00 |
|
Jingrong Lin
|
77b188060b
|
Merge branch 'master' into preloading_clean
|
2024-09-11 11:08:49 +08:00 |
|
Lin
|
ae6a8cb604
|
fix bug
|
2024-09-10 14:34:42 +08:00 |
victorzh001
|
04a60ca4b5
|
Merge branch 'master' into victor_OpenFPGA_dbg
|
2024-09-10 11:01:47 +08:00 |
Victor
|
3ea830e168
|
Add the reference_file to the index.rst
|
2024-09-10 10:46:15 +08:00 |
|
tangxifan
|
7250a7d703
|
[core] code format
|
2024-09-09 12:46:46 -07:00 |
|
tangxifan
|
e3b99e88ff
|
[core] syntax
|
2024-09-09 12:46:23 -07:00 |
|
tangxifan
|
fc92ecea24
|
[core] typo
|
2024-09-09 12:43:38 -07:00 |
|
tangxifan
|
5f50e4623c
|
[core] add a new option map_global_net_to_msb for pb_pin_fixup
|
2024-09-09 12:21:09 -07:00 |
|
Lin
|
f1547bae8a
|
fix build error
|
2024-09-09 18:18:07 +08:00 |
|
tangxifan
|
37cac3d679
|
Merge branch 'master' into victor_OpenFPGA_dbg
|
2024-09-08 21:13:48 -07:00 |
|
Lin
|
41d0eb7736
|
modification on device_rr_gsb
|
2024-09-09 11:36:48 +08:00 |
|
Lin
|
af7201d4bb
|
fix is_compressed_ tag
|
2024-09-09 11:19:12 +08:00 |