tangxifan
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70734abc35
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[Arch] Remove QN from stdcell arch
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2020-11-06 11:20:13 -07:00 |
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tangxifan
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1a79a55646
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[HDL] Add DFF cell with reset but only 1 output
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2020-11-06 11:19:19 -07:00 |
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tangxifan
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0a273ffab6
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[Tool] Bug fix in the tight requirements on CCFF circuit model
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2020-11-06 11:16:46 -07:00 |
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tangxifan
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ba0120bd76
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[Tool] Remove the limitation on requiring Qb ports for CCFF
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2020-11-06 11:10:04 -07:00 |
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tangxifan
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2aab8bf910
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[Arch] Use single-output DFF for a standard cell FPGA
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2020-11-06 10:26:39 -07:00 |
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tangxifan
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7d46b35296
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[HDL] Add single-output DFF HDL
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2020-11-06 10:18:37 -07:00 |
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tangxifan
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55b14fa6b4
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Merge branch 'master' of https://github.com/LNIS-Projects/OpenFPGA into dev
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2020-11-06 10:11:38 -07:00 |
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tangxifan
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4a53640cf8
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Merge pull request #117 from olofk/patch-1
Update README.md
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2020-11-06 09:21:18 -07:00 |
Olof Kindgren
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468c3ff353
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Update README.md
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2020-11-06 09:53:11 +01:00 |
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tangxifan
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849ecc7fc0
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[Doc] Add notes for using the is_data_io syntax
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2020-11-05 09:30:19 -07:00 |
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tangxifan
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9bce2f3818
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[Doc] Update documentation for new XML syntax "is_data_io"
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2020-11-05 09:28:46 -07:00 |
Laboratory for Nano Integrated Systems (LNIS)
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55f7a2c187
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Merge pull request #116 from LNIS-Projects/dev
Extended I/O Support for SoC I/O interface
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2020-11-04 21:55:37 -07:00 |
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tangxifan
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93e7107d80
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[Test] Add new test to CI
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2020-11-04 20:59:34 -07:00 |
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tangxifan
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bce8233019
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[Arch] Bug fix in caravel arch
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2020-11-04 20:58:58 -07:00 |
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tangxifan
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6b48ee7f0b
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[Test] Add new test for caravel io support
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2020-11-04 20:58:40 -07:00 |
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tangxifan
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c85edb4738
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[Arch] Bug fix for embedded io arch
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2020-11-04 20:52:47 -07:00 |
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tangxifan
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9b0617ffe6
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[Tool] Bug fix for mappable I/O support
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2020-11-04 20:45:51 -07:00 |
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tangxifan
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a6c7bb2c48
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[Arch] Update OpenFPGA arch for new syntax on I/O
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2020-11-04 20:24:02 -07:00 |
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tangxifan
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37c10f0cb5
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[Tool] Add mappable I/O support and enhance I/O support
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2020-11-04 20:21:49 -07:00 |
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tangxifan
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dd86f7f464
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[Arch] Path architecture for caravel i/o interface
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2020-11-04 17:16:21 -07:00 |
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tangxifan
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c074e88dcd
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[HDL] Add embedded I/O HDL for Caravel SoC interface
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2020-11-04 17:09:59 -07:00 |
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tangxifan
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aebf7453d0
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[Arch] Add architecture files with compatible I/O capacity with caravel SoC
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2020-11-04 16:57:00 -07:00 |
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tangxifan
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19f2bf9b38
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[Test] deploy new test cases to CI
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2020-11-04 16:35:51 -07:00 |
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tangxifan
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61376a2979
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[Test] Add test cases for various tile organization
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2020-11-04 16:32:52 -07:00 |
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tangxifan
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cf455df555
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[Arch] Add architecture for bottom-right and top-left tile organization
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2020-11-04 16:24:36 -07:00 |
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tangxifan
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46ca406f10
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[Arch] Add a new vpr architecture with new tile organization
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2020-11-04 16:20:01 -07:00 |
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tangxifan
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049ca14461
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[Doc] Add new naming rules for vpr architecture files
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2020-11-04 16:17:56 -07:00 |
|
Laboratory for Nano Integrated Systems (LNIS)
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1f3e656f2e
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Merge pull request #115 from LNIS-Projects/dev
Refactor the codes for walking through io blocks
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2020-11-04 12:54:07 -07:00 |
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tangxifan
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4a2874b2bc
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[Tool] Refactor the codes for walking through io blocks
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2020-11-03 13:21:50 -07:00 |
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Laboratory for Nano Integrated Systems (LNIS)
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5d41cc6d23
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Merge pull request #114 from LNIS-Projects/dev
Support I/O interfaces for Embedded FPGAs
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2020-11-02 21:10:52 -07:00 |
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tangxifan
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c036c87d6d
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[HDL] Bug fix in the GP output pad
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2020-11-02 18:37:53 -07:00 |
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tangxifan
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1e47203c7c
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[Tool] Auto-generated gate Verilog netlist should not contain any signal initalization
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2020-11-02 18:35:26 -07:00 |
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tangxifan
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e4d974c5c8
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[Tool] Split io location mapping builder from fabric builder
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2020-11-02 18:27:34 -07:00 |
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tangxifan
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1fd899ecee
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[Tool] Relex logic block checking codes to skip zero-capacity nodes
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2020-11-02 16:57:19 -07:00 |
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tangxifan
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3b49e6d090
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[Arch] Patch embedded IO architecture by forcing only 1 pad per block
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2020-11-02 15:39:31 -07:00 |
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tangxifan
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c512644a09
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[Arch] Patch embedded I/O example architecture
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2020-11-02 15:16:19 -07:00 |
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tangxifan
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7e9e0ec9d4
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[HDL] Bug fix in I/O HDL code
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2020-11-02 15:15:45 -07:00 |
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tangxifan
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f1ce816d6c
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[Tool] Force inout port to be mandatory for I/O cells
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2020-11-02 15:14:02 -07:00 |
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tangxifan
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2f237a6240
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[HDL] Add HDL codes for embedded I/Os
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2020-11-02 14:01:27 -07:00 |
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tangxifan
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55b77ac6cb
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[Arch] Bug fixed in embedded FPGA architecture
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2020-11-02 13:57:15 -07:00 |
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tangxifan
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e850dd5314
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[Tool] Relax checking codes for embedded I/O circuit models
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2020-11-02 13:54:31 -07:00 |
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tangxifan
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a7e7fa2005
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[Arch] Update arch with true embedded I/O definition
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2020-11-02 13:29:40 -07:00 |
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tangxifan
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65ca53ac98
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[Test] Update test case with the new arch name
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2020-11-02 13:16:42 -07:00 |
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tangxifan
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8c8190047f
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[Arch] Rename architecture files for embedded I/Os
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2020-11-02 13:15:19 -07:00 |
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tangxifan
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a346c529aa
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[Test] Deploy test case to CI
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2020-11-02 12:29:20 -07:00 |
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tangxifan
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bc00dee858
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[Test] Add test case for embedded I/O
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2020-11-02 12:28:25 -07:00 |
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tangxifan
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f86f43d287
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[Arch] Add openfpga architecture file for constrained pin equivalence
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2020-11-02 12:27:40 -07:00 |
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tangxifan
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795b30f76b
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[Arch] Add VPR architecture with partial pin equivalence
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2020-11-02 11:54:25 -07:00 |
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tangxifan
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032cbfb8b2
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Merge pull request #113 from LNIS-Projects/dev
Multi-region support on Frame-based Configuration Protocol
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2020-10-31 10:37:38 -06:00 |
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tangxifan
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be7f7592ae
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[Doc] Update documentation about don't care bit in frame address
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2020-10-30 22:13:28 -06:00 |