tangxifan
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867da98d3f
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[core] update to use latest api from vpr upstream
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2023-08-08 16:28:19 -07:00 |
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tangxifan
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cb4512b925
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[core] code format
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2023-04-19 11:10:42 +08:00 |
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tangxifan
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a84cc52d7c
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[core] fixed a few bugs due to the changes in vtr regarding flat router
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2023-04-19 11:08:18 +08:00 |
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tangxifan
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bffb4eedc9
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[engine] typo
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2022-12-30 18:18:51 -08:00 |
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tangxifan
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d329f0bb44
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[engine] code format
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2022-12-30 18:17:19 -08:00 |
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tangxifan
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5c4e749b95
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[engine] add standalone vpr commands
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2022-12-30 18:12:51 -08:00 |
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tangxifan
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6d31b319a2
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[engine] update source files subject to code formatting rules
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2022-10-06 17:08:50 -07:00 |
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tangxifan
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b3e4a06969
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[engine] adapt vpr wrapper to the latest main.cpp from vtr
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2022-08-23 14:28:05 -07:00 |
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tangxifan
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4a05cec037
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add rr_segment binding to circuit model
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2020-02-12 11:21:40 -07:00 |
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tangxifan
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b8c504f574
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Do not allow vpr to free everything when it is done. So that we can have access to their device data
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2020-01-27 19:49:05 -07:00 |
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tangxifan
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5ecb771673
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debugging the annotation to physical mode of pb_types
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2020-01-27 17:43:22 -07:00 |
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tangxifan
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cdb3b6de46
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add read_openfpga_arch to OpenFPGA shell
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2020-01-23 19:10:53 -07:00 |