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2675 Commits

Author SHA1 Message Date
tangxifan 3d234d840b [Documentation] Update documentation for the edge triggered attribute 2020-09-23 20:31:11 -06:00
tangxifan 064678fe32 [OpenFPGA Tool] Add edge triggered attribute to circuit library definition. Better support for using CCFF in frame-based protocol 2020-09-23 20:27:52 -06:00
tangxifan 8e4e66038a [Architecture] Bug fix for standalone memory 2020-09-23 19:32:48 -06:00
tangxifan 437ef54431 [Regression Test] Bug fix for CI 2020-09-23 19:20:41 -06:00
tangxifan ad881ea4dc [OpenFPGA Tool] Bug fix for Verilog testbench using frame-based /memory bank 2020-09-23 18:59:25 -06:00
tangxifan 129caea38c [Architecture] Patch configurable latch Verilog HDL with resetb 2020-09-23 18:30:48 -06:00
tangxifan 1864b080a2 [Architecture] Bug fix in configurable latch Verilog HDL 2020-09-23 18:28:45 -06:00
tangxifan 9adeb550dc [OpenFPGA Tool] Bug fix in fabric builder 2020-09-23 18:28:00 -06:00
tangxifan 341a757831 [Regression Test] Deploy configuration frame using ccff test case to CI 2020-09-23 18:05:55 -06:00
tangxifan ebb866d04a [Architecture] Patch frame based using ccff 2020-09-23 18:04:14 -06:00
tangxifan 906191e931 [Architecture] Use strict latch Verilog HDL in frame-based procotol 2020-09-23 17:58:13 -06:00
tangxifan 645db17168 [Architecture] Patch DFF Verilog HDL 2020-09-23 17:52:59 -06:00
tangxifan 092ada39f4 [Architecture] Add Verilog HDL for DFF with write enable 2020-09-23 17:49:30 -06:00
tangxifan ad385c6d69 [Regression Test] Add test case for using SRAM cell in frame-based configuration 2020-09-23 17:39:36 -06:00
tangxifan 1a2c66f07d [Architecture] Add openfpga architecture where frame-based configuration procotol uses a SRAM cell 2020-09-23 17:34:49 -06:00
tangxifan f0d31f50f4 [Regression Test] Deploy active-low configurable latch test case to CI 2020-09-23 17:28:36 -06:00
tangxifan a3c982a83f [Architecture] Patch the openfpga architecture using active-low configurable latch 2020-09-23 17:27:16 -06:00
tangxifan f23c25e123 [Regression Test] Add test case for configurable latch with active-low reset 2020-09-23 17:25:17 -06:00
tangxifan a94c2655c2 [Architecture] Patch Verilog HDL for configurable latch 2020-09-23 17:21:30 -06:00
tangxifan 893859be37 [Architecture] Add openfpga architecture using active-low configurable latch 2020-09-23 17:21:00 -06:00
tangxifan b242ab79bd [OpenFPGA Flow] Add Verilog HDL for configurable latch with active-low reset 2020-09-23 17:19:02 -06:00
tangxifan 5c62bafa7f [Regression Test] Deploy the fix device test case to CI 2020-09-23 16:48:45 -06:00
tangxifan 149d5b20bd [Regression Test] Add test case for fixed device support 2020-09-23 16:47:11 -06:00
tangxifan c92cf71891 [Regression Test] Add a new template script for fixed device support 2020-09-23 16:46:41 -06:00
tangxifan 6ed05d380b [Regression Test] Deploy pattern based local routing test case to CI 2020-09-23 16:08:01 -06:00
tangxifan 3350695806 [Regression test] Add test case for pattern based local routing architecture 2020-09-23 16:06:47 -06:00
tangxifan 1aab691e9d [Architecture] Add openfpga architecture using pattern based local routing 2020-09-23 16:06:16 -06:00
tangxifan 951a47b19c [Architecture] Add k4 series architecture using pattern-based local routing 2020-09-23 16:05:39 -06:00
ganeshgore 32c43ffb90 Script cleanup 2020-09-23 14:06:33 -06:00
ganeshgore e31589f9b6 Merge remote-tracking branch 'lnis_origin/master' into ganesh_dev 2020-09-23 14:03:25 -06:00
tangxifan 6480b06a2d [OpenFPGA tool] Remove out-of-data test blif, architecture and scripts 2020-09-23 11:01:53 -06:00
Laboratory for Nano Integrated Systems (LNIS) d32998b9ec
Merge pull request #91 from LNIS-Projects/dev 
[Regression Tests] Remove deadlink
 2020-09-22 23:27:11 -06:00
tangxifan 7729f671ab [Regression Tests] Remove deadlink 2020-09-22 18:35:41 -06:00
Laboratory for Nano Integrated Systems (LNIS) 9515d2310a
Merge pull request #90 from LNIS-Projects/dev 
Architecture and regression test update
 2020-09-22 16:11:06 -06:00
tangxifan 8f4cca789a [Regression Test] Add k4n4 with fracturable multiplier test case to CI 2020-09-22 15:34:44 -06:00
tangxifan 51c0319657 [Regression tests] Add test case for the k4n4 with fracturable 32-bit multiplier 2020-09-22 15:32:54 -06:00
tangxifan 70b8b02f74 [Architecture] Add vpr architecture for k4n4 with fracturable 32-bit multiplier 2020-09-22 15:32:11 -06:00
tangxifan 72749be4bd [Architecture] Add OpenFPGA architecture for k4n4 with fracturable 32-bit multiplier 2020-09-22 15:31:34 -06:00
tangxifan 61bcbaafd8 [Architecture] Add Verilog HDL for fracturable 32-bit multiplier 2020-09-22 15:15:19 -06:00
tangxifan a61d161cbe [Regression Test] Deploy k4n4 with multiple segments to CI 2020-09-22 12:48:53 -06:00
tangxifan 3d1f49fb2f [Regression Test] Add testcase for k4n4 with multiple segments 2020-09-22 12:47:41 -06:00
tangxifan 801055b007 [OpenFPGA Tool] Bug Fix on the tileable RRG for multi segment 2020-09-22 12:47:02 -06:00
tangxifan 13df6c1c21 [Architecture] Add openfpga architecture for k4n4 using multiple segments 2020-09-22 12:36:11 -06:00
tangxifan 8a3934b749 [Architecture Add vpr architecture for k4n4 using multiple wire segments 2020-09-22 12:35:39 -06:00
tangxifan 8fff2b77eb [Regression Test] Deploy k4n4 BRAM test case to CI 2020-09-22 12:24:54 -06:00
tangxifan 5741664580 [Regression Test] Add test case for k4n4 bram architecture 2020-09-22 12:23:56 -06:00
tangxifan ddf999b6b9 [Architecture] Add verilog HDL for dual-port BRAM 1k 2020-09-22 12:23:28 -06:00
tangxifan 26fba4a94b [Architecture] Add openfpga architectue for k4n4 with bram blocks 2020-09-22 12:22:59 -06:00
tangxifan daf776b7b1 [Architecture] Add k4n4 architecture with bram block for basic tests 2020-09-22 12:22:32 -06:00
tangxifan 237fc2e636 [Regression test] Deploy no local routing in basic tests to CI 2020-09-22 11:49:16 -06:00