tangxifan
|
93ebbef851
|
[core] fixed a bug
|
2024-05-31 19:42:50 -07:00 |
tangxifan
|
86a5f905d1
|
Merge branch 'xt_wlut' of github.com:lnis-uofu/OpenFPGA into xt_wlut
|
2024-05-31 18:03:00 -07:00 |
tangxifan
|
514ec2f02e
|
[core] code format
|
2024-05-31 18:02:46 -07:00 |
tangxifan
|
f46c132774
|
Merge branch 'master' into xt_wlut
|
2024-05-31 18:02:10 -07:00 |
tangxifan
|
2d10be9edb
|
[core] code comments
|
2024-05-31 18:00:24 -07:00 |
tangxifan
|
f9cd01636d
|
[core] fixed the bug where there is only 1 routing trace for a net which should be ignored (due to treated as global). This net should not be ignored unless there are >1 routing traces on the top-level pb. Then we can merge one.
|
2024-05-31 17:57:36 -07:00 |
tangxifan
|
212abecc27
|
[core] syntax
|
2024-05-31 17:41:49 -07:00 |
tangxifan
|
348d474bfd
|
[core] more debuggin messages
|
2024-05-31 17:40:19 -07:00 |
tangxifan
|
c565264e7d
|
[core] more debuggin messages
|
2024-05-31 17:14:42 -07:00 |
tangxifan
|
a60ffd4953
|
Merge pull request #1687 from lnis-uofu/patch_update
Pulling refs/heads/master into master
|
2024-05-31 17:04:37 -07:00 |
github-actions[bot]
|
7ede31a61f
|
Updated Patch Count
|
2024-06-01 00:02:49 +00:00 |
tangxifan
|
6dc31bf892
|
[core] fixed a bug on missing net sync up during repack
|
2024-05-31 16:53:59 -07:00 |
tangxifan
|
5b35f567d2
|
[core] detailed messages to trace why some nets are no sync
|
2024-05-31 16:00:10 -07:00 |
tangxifan
|
5adc1be204
|
[core] syntax
|
2024-05-31 15:50:27 -07:00 |
tangxifan
|
a9ccc277bd
|
[core] more debugging message
|
2024-05-31 15:49:34 -07:00 |
tangxifan
|
937e279c59
|
[core] adding more debugging messages
|
2024-05-31 15:43:51 -07:00 |
tangxifan
|
7a7fc679a8
|
[core] enable more debugging message in repacker
|
2024-05-31 14:52:59 -07:00 |
tangxifan
|
edb50f1b4d
|
[core] update debug messages
|
2024-05-31 14:37:46 -07:00 |
tangxifan
|
3a14a59a8e
|
[ci] now reg tests are only run on PR for main branch
|
2024-05-31 12:46:28 -07:00 |
tangxifan
|
48c0b4b219
|
[core] fixed a bug where net name is not shown correctly on wire LUTs
|
2024-05-31 12:45:12 -07:00 |
tangxifan
|
d82f1efd8b
|
Merge pull request #1686 from lnis-uofu/dependabot/submodules/yosys-a84e4f4
Bump yosys from `5579685` to `a84e4f4`
|
2024-05-31 10:02:28 -07:00 |
dependabot[bot]
|
3fcd02b841
|
Bump yosys from `5579685` to `a84e4f4`
Bumps [yosys](https://github.com/YosysHQ/yosys) from `5579685` to `a84e4f4`.
- [Release notes](https://github.com/YosysHQ/yosys/releases)
- [Commits](5579685673...a84e4f44fe )
---
updated-dependencies:
- dependency-name: yosys
dependency-type: direct:production
...
Signed-off-by: dependabot[bot] <support@github.com>
|
2024-05-31 06:43:59 +00:00 |
tangxifan
|
90dc5d7941
|
Merge pull request #1685 from lnis-uofu/patch_update
Pulling refs/heads/master into master
|
2024-05-29 14:36:56 -07:00 |
github-actions[bot]
|
43ec1dd596
|
Updated Patch Count
|
2024-05-29 21:36:28 +00:00 |
tangxifan
|
90a918ca91
|
Merge pull request #1684 from lnis-uofu/xt_doc
Fixed a critical bug in GSB XML writer which causes mismatches against netlist. Fixed typos in documentation
|
2024-05-29 13:22:45 -07:00 |
tangxifan
|
b491ba03b7
|
[doc] typo
|
2024-05-29 10:33:39 -07:00 |
tangxifan
|
8f2974d7a1
|
[test] update golden copies
|
2024-05-29 10:31:19 -07:00 |
tangxifan
|
74e94b855e
|
[core] fixed a bug where gsb OPIN name does not match the switch block module
|
2024-05-29 10:27:10 -07:00 |
tangxifan
|
32c52371f1
|
Merge pull request #1683 from lnis-uofu/patch_update
Pulling refs/heads/master into master
|
2024-05-28 18:03:23 -07:00 |
github-actions[bot]
|
21579128b9
|
Updated Patch Count
|
2024-05-29 00:02:43 +00:00 |
tangxifan
|
572860714c
|
Merge pull request #1682 from lnis-uofu/dependabot/submodules/yosys-5579685
Bump yosys from `c71262f` to `5579685`
|
2024-05-28 15:36:40 -07:00 |
dependabot[bot]
|
0a922b6504
|
Bump yosys from `c71262f` to `5579685`
Bumps [yosys](https://github.com/YosysHQ/yosys) from `c71262f` to `5579685`.
- [Release notes](https://github.com/YosysHQ/yosys/releases)
- [Commits](c71262f66b...5579685673 )
---
updated-dependencies:
- dependency-name: yosys
dependency-type: direct:production
...
Signed-off-by: dependabot[bot] <support@github.com>
|
2024-05-27 06:09:54 +00:00 |
tangxifan
|
2196fc4697
|
Merge pull request #1681 from lnis-uofu/patch_update
Pulling refs/heads/master into master
|
2024-05-23 11:42:07 -07:00 |
github-actions[bot]
|
043c9c4c20
|
Updated Patch Count
|
2024-05-23 18:41:16 +00:00 |
tangxifan
|
f308378a25
|
Merge pull request #1680 from lnis-uofu/dependabot/submodules/yosys-c71262f
Bump yosys from `7045cf5` to `c71262f`
|
2024-05-23 11:40:44 -07:00 |
dependabot[bot]
|
2593cb2e3c
|
---
updated-dependencies:
- dependency-name: yosys
dependency-type: direct:production
...
Signed-off-by: dependabot[bot] <support@github.com>
|
2024-05-22 06:34:22 +00:00 |
tangxifan
|
286eacd601
|
Merge pull request #1679 from lnis-uofu/patch_update
Pulling refs/heads/master into master
|
2024-05-21 14:16:05 -07:00 |
github-actions[bot]
|
eb150154e8
|
Updated Patch Count
|
2024-05-21 21:06:55 +00:00 |
tangxifan
|
9fa3b53aab
|
Merge pull request #1678 from lnis-uofu/xt_ecb
Support Enhanced Connection Block
|
2024-05-21 14:04:12 -07:00 |
tangxifan
|
d31e3bb8bf
|
Merge branch 'xt_ecb' of github.com:lnis-uofu/OpenFPGA into xt_ecb
|
2024-05-21 11:14:27 -07:00 |
tangxifan
|
391b768b3a
|
[doc] syntax
|
2024-05-21 11:14:12 -07:00 |
tangxifan
|
d5ffb44417
|
Merge branch 'master' into xt_ecb
|
2024-05-21 11:06:28 -07:00 |
tangxifan
|
2155d42dc0
|
Merge pull request #1677 from lnis-uofu/dependabot/submodules/vtr-verilog-to-routing-ec85a46
Bump vtr-verilog-to-routing from `48c0303` to `ec85a46`
|
2024-05-21 11:05:54 -07:00 |
tangxifan
|
4c6b923b74
|
[doc] add a figure about ecb
|
2024-05-21 11:03:58 -07:00 |
tangxifan
|
5775187072
|
[doc] enhance connection block details and restrictions
|
2024-05-21 10:55:13 -07:00 |
dependabot[bot]
|
8069579095
|
---
updated-dependencies:
- dependency-name: vtr-verilog-to-routing
dependency-type: direct:production
...
Signed-off-by: dependabot[bot] <support@github.com>
|
2024-05-21 06:27:54 +00:00 |
tangxifan
|
3c49af6a08
|
[test] code format
|
2024-05-20 21:28:46 -07:00 |
tangxifan
|
f25081eb31
|
[test] add a new test to validate ecb when tile modules are used
|
2024-05-20 21:10:49 -07:00 |
tangxifan
|
852b01aaff
|
[test] rework
|
2024-05-20 17:20:04 -07:00 |
tangxifan
|
d3d29a507f
|
[lib] update vtr
|
2024-05-20 17:17:10 -07:00 |