tangxifan
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6d31b319a2
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[engine] update source files subject to code formatting rules
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2022-10-06 17:08:50 -07:00 |
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tangxifan
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001367ea41
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[engine] syntax
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2022-09-01 16:40:17 -07:00 |
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tangxifan
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1f5e4d4215
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[engine] update fabric bitstream implementation
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2022-09-01 16:29:42 -07:00 |
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tangxifan
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ffac5a66e1
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[FPGA-Bitstream] Now encode address bits to save memory in bitstream database
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2022-05-25 17:45:08 +08:00 |
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tangxifan
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386812777c
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[FPGA-Bitstream] Upgraded bitstream writer to support flatten BL/WLs
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2021-09-25 12:49:32 -07:00 |
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tangxifan
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1a2a2a6e63
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[FPGA-Bitstream] Relax fabric bitstream address check
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2021-09-25 12:03:33 -07:00 |
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tangxifan
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9a441fa5cc
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[Tool] Upgrade openfpga to support extended global tile port definition
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2021-01-09 18:47:12 -07:00 |
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tangxifan
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b78f8bec16
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[Tool] Bug fixed for multi-region configuration frame
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2020-10-30 21:19:20 -06:00 |
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tangxifan
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e988e35f81
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[Tool] Support region-based bitstream in fabric bitstream data base and Verilog testbenches
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2020-09-29 12:22:10 -06:00 |
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tangxifan
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180d72f3e5
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[Tool] Add regions to fabric bitstream
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2020-09-28 21:04:08 -06:00 |
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tangxifan
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2a9377b3f4
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use encoded address in storage of fabric bitstream to save memory
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2020-07-03 15:12:29 -06:00 |
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tangxifan
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6ea857ae6c
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use fast method to inquire number of bits and blocks in bitstream databases
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2020-07-03 10:55:25 -06:00 |
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tangxifan
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7ca1a5bdc1
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Fabric bitstream now allocates vectors in conditions for memory efficiency
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2020-07-03 10:17:03 -06:00 |
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tangxifan
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8a45e48a1c
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minor fix
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2020-07-02 22:27:48 -06:00 |
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tangxifan
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dee4be96af
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reserve all the input/output net storage in bitstream manager
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2020-07-02 19:17:34 -06:00 |
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tangxifan
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81c9fcb7c0
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bug fix when optimizing the fabric bitstream data structure
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2020-07-02 16:41:32 -06:00 |
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tangxifan
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9608cefa86
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remove id vector in fabric bitstream database and replace with more memory efficient implementation
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2020-07-02 16:08:50 -06:00 |
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tangxifan
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9f19c36a89
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use char in fabric bitstream to save memory footprint
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2020-07-02 15:56:50 -06:00 |
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tangxifan
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b85af57971
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optimizing fabric bitsteream memory footprint
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2020-07-02 12:39:18 -06:00 |
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tangxifan
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51e1559352
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add fabric bitstream support for memory bank configuration protocol
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2020-06-11 19:31:13 -06:00 |
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tangxifan
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cff5b5cfc1
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break the configuration testbench. This commit is to spot which modification leads to the problem
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2020-06-11 19:31:10 -06:00 |
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tangxifan
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4a0e1cd908
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add fabric bitstream data structure and deploy it to Verilog testbench generation
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2020-06-11 19:31:10 -06:00 |
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tangxifan
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8c14cced84
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start improve fabric bitstream database to support frame-based configuration protocol
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2020-06-11 19:31:09 -06:00 |