tangxifan
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62e4f14e30
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add lb_rr_graph to device annotation
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2020-02-17 17:26:27 -07:00 |
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tangxifan
|
6c69b52ded
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Add missing file
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2020-02-17 17:11:29 -07:00 |
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tangxifan
|
8b0df8632c
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bring fpga verilog create directory online
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2020-02-15 20:38:45 -07:00 |
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tangxifan
|
213c611c0b
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add tile direct builder
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2020-02-14 22:21:32 -07:00 |
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tangxifan
|
f11832b8cf
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start integrating module graph builder
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2020-02-12 17:53:23 -07:00 |
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tangxifan
|
c78d3e9af1
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add mux library builder
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2020-02-12 14:58:23 -07:00 |
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tangxifan
|
a31d6c6d1e
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rename pb_type annotation to device annotation
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2020-02-12 09:52:18 -07:00 |
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tangxifan
|
1372f748f1
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put GSB builder online
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2020-02-11 16:37:14 -07:00 |
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tangxifan
|
dad204674b
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done an initial version of clustering net fix-up based on routing results. Debugging on the way
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2020-02-05 21:50:52 -07:00 |
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tangxifan
|
2dc4c26257
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add naming fix-up
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2020-01-29 17:49:33 -07:00 |
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tangxifan
|
a6fbbce33e
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start developing the openfpga arch binding to vpr
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2020-01-27 15:31:12 -07:00 |
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tangxifan
|
cdb3b6de46
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add read_openfpga_arch to OpenFPGA shell
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2020-01-23 19:10:53 -07:00 |
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tangxifan
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ba207ee5a5
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start split workload from the main.cpp in openfpga
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2020-01-23 13:24:35 -07:00 |