tangxifan
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96f36a96dd
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[core] syntax
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2023-09-25 16:50:30 -07:00 |
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tangxifan
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0a94763422
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[lib] add module rename assistant
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2023-09-22 18:16:01 -07:00 |
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tangxifan
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278b8e2409
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[lib] fixed a typo which causes outputted module name XMLs carry syntax errors
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2023-09-22 17:37:27 -07:00 |
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tangxifan
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c6175aa514
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[core] code format
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2023-09-17 22:37:48 -07:00 |
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tangxifan
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ef97127c63
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[core] fixed some bugs in testbenches when renaming top modules
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2023-09-17 22:34:00 -07:00 |
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tangxifan
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72a3c05747
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[core] code format
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2023-09-17 13:29:30 -07:00 |
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tangxifan
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ccd4c1861b
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[core] developing new command to write module naming rules
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2023-09-16 19:37:06 -07:00 |
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tangxifan
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37573abc22
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[core] code format
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2023-09-15 23:32:40 -07:00 |
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tangxifan
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bc407e5d69
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[core] code complete for rename modules
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2023-09-15 23:22:31 -07:00 |
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tangxifan
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7913e6cc6a
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[lib] update tests and fixed some bugs
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2023-09-15 17:38:51 -07:00 |
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tangxifan
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b5cf08a3c5
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[lib] add testing
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2023-09-15 17:15:05 -07:00 |
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tangxifan
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74b9f673ec
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[lib] syntax and add missing api
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2023-09-15 17:00:02 -07:00 |
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tangxifan
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636647902e
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[lib] developing io for module name map
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2023-09-15 16:53:24 -07:00 |
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tangxifan
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e5bc936144
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[lib] developing io
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2023-09-15 16:19:10 -07:00 |
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tangxifan
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b65dda90c4
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[lib] developing naming manager
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2023-09-15 16:02:13 -07:00 |
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tangxifan
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af67b02cca
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[lib] rename lib to namemanager as a unified library to provide naming support on FPGA modules
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2023-09-15 13:51:14 -07:00 |