tangxifan
|
8f5a684b10
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removed redundant include files in all the verilog netlists except the top one
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2020-06-11 19:28:13 -06:00 |
ganeshgore
|
773790bc2c
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Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
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2020-04-24 11:00:40 -06:00 |
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tangxifan
|
e811f8bb21
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plug in netlist manager and now the include_netlist appears in one unique file
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2020-04-23 20:42:11 -06:00 |
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tangxifan
|
87b17fc25f
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add netlist manager data structure
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2020-04-23 18:59:09 -06:00 |
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tangxifan
|
90f608baea
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changing task mcnc file for debugging (temporarily now) Will be corrected later
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2020-04-23 18:58:39 -06:00 |
|
tangxifan
|
417d534121
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fine tune mcnc example script to run Modelsim simulations easily
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2020-04-23 16:15:45 -06:00 |
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ganeshgore
|
ca793285ca
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Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
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2020-04-23 12:18:24 -06:00 |
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tangxifan
|
df85175765
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fine tuning on mcnc example script so that we can run run_modelsim.py --runsim
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2020-04-22 21:44:52 -06:00 |
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tangxifan
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f9fcc6b471
|
tweak mcnc scripts by stop VRP to remove buffers. Now passed mcnc big20 in Verilog/Bitstream generation
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2020-04-22 18:24:09 -06:00 |
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tangxifan
|
0c4904065f
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reduce activity error to warning.
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2020-04-22 17:36:02 -06:00 |
|
tangxifan
|
bf841b9a8e
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bug fixed in identifying wired LUT
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2020-04-22 17:28:16 -06:00 |
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tangxifan
|
341f38025e
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add spypad to regression test
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2020-04-22 14:42:30 -06:00 |
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tangxifan
|
8ac6e10727
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bug fix in lut and mux module generation on supporting spypads
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2020-04-22 14:41:16 -06:00 |
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tangxifan
|
726185cd5e
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add test cases using spypad architecture
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2020-04-22 12:56:57 -06:00 |
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tangxifan
|
73e9006372
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add arch file with spy pads
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2020-04-22 12:56:09 -06:00 |
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tangxifan
|
9fb8971281
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add FPGA arch with spypads to portofilo
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2020-04-22 11:12:28 -06:00 |
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tangxifan
|
9960625b01
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add example spypad architecture
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2020-04-22 11:10:59 -06:00 |
|
Xifan Tang
|
52adebacfb
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update doc for file options in openfpga bitstream
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2020-04-21 14:40:53 -06:00 |
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tangxifan
|
2e3054f79a
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bug fixed for SDC generation for LUTs
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2020-04-21 14:34:51 -06:00 |
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tangxifan
|
68b7991a46
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bug fixed for sdc on memory blocks
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2020-04-21 13:37:56 -06:00 |
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tangxifan
|
d325bede68
|
add fabric bitstream writer
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2020-04-21 12:02:10 -06:00 |
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tangxifan
|
3f1fb70d16
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FPGA SDC now constrain max and min delay for primitive modules in grids
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2020-04-21 11:00:28 -06:00 |
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tangxifan
|
c2804a4c1f
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bug fix for RC delay computing in SDC generation
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2020-04-20 22:20:00 -06:00 |
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tangxifan
|
1a8968cb37
|
now FPGA-SDC will constrain timing for routing tracks using the VPR Rmetal parameter in ARCH XML
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2020-04-20 21:12:51 -06:00 |
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tangxifan
|
9761d13eef
|
update microbenchmark and2 module name
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2020-04-20 13:37:39 -06:00 |
|
tangxifan
|
f06f2d72be
|
deploy single mode in regression tests
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2020-04-20 13:16:52 -06:00 |
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tangxifan
|
489ca75230
|
adapt benchmark and_latch module name to be different than benchmark and
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2020-04-20 13:15:05 -06:00 |
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tangxifan
|
f6b7583a2a
|
add tasks for single mode
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2020-04-20 12:55:40 -06:00 |
|
tangxifan
|
8b03ec900f
|
fine-tune micro benchmark to fit port mapping in testbenches
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2020-04-19 17:05:12 -06:00 |
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tangxifan
|
e10cafe0a5
|
Critical patch on repacking about wire LUT support.
Previously, the wire LUT identification is too naive and does not consider all the cases
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2020-04-19 16:42:31 -06:00 |
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tangxifan
|
32ed609238
|
update micro benchmark set and regression tests using them
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2020-04-19 12:49:07 -06:00 |
|
tangxifan
|
98878f474b
|
light change on arch file to accelerate mcnc big20 run
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2020-04-19 12:03:31 -06:00 |
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tangxifan
|
cc163081f5
|
recover mcnc big20 test configuration
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2020-04-18 21:06:43 -06:00 |
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tangxifan
|
2e3a811f4f
|
critical bug fixed in repacking. This is due to depop50% local routing where the same net may be mapped to two different pins in the same pb_graph_pin. Now we restrict the pin searching. But in long term, we should sync the pb_route results to post routing results
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2020-04-18 21:04:46 -06:00 |
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tangxifan
|
f76a3090c4
|
add mcnc big20 test cases and start debugging
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2020-04-18 19:25:16 -06:00 |
|
tangxifan
|
95863e996a
|
minor update on arch to use auto layout sizing
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2020-04-18 18:43:56 -06:00 |
|
tangxifan
|
2f3a36ee81
|
update timing and rename the arch file
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2020-04-18 18:39:47 -06:00 |
|
tangxifan
|
7ce34be175
|
update sample architecture timing
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2020-04-17 22:06:06 -06:00 |
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tangxifan
|
2ea4b8a2a2
|
add more flagship architectures
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2020-04-17 19:12:27 -06:00 |
|
ganeshgore
|
7e7001e993
|
Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
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2020-04-15 20:56:13 -06:00 |
|
tangxifan
|
a7d900088b
|
now generating simulation ini file will try to create directory first
|
2020-04-15 20:53:37 -06:00 |
|
tangxifan
|
72e8824a87
|
bug fixed on removing undriven pins (direct connection between clbs) from cb
|
2020-04-15 20:41:15 -06:00 |
|
tangxifan
|
2ffd174e6a
|
fixed a bug in single mode FPGA; add arch to regression test; deploy full testbench verification on Travis CI
|
2020-04-15 15:48:33 -06:00 |
|
tangxifan
|
032ebc29e6
|
Merge branch 'ganesh_dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
|
2020-04-15 12:53:20 -06:00 |
|
tangxifan
|
1e742a3676
|
add test case on auto-check test benches
|
2020-04-15 12:52:52 -06:00 |
|
ganeshgore
|
689c4a3e19
|
BugFix: The filename in the previous commit
|
2020-04-15 12:44:22 -06:00 |
|
tangxifan
|
46fe1e84ce
|
Merge branch 'dev' into ganesh_dev
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2020-04-15 12:27:51 -06:00 |
|
ganeshgore
|
7f37bf1441
|
Added formal verification support to fpga_flow script
|
2020-04-15 12:24:51 -06:00 |
|
tangxifan
|
56e0d2a918
|
critical patch on the ccff head and tail connection in grid modules for VPR7+OpenFPGA
|
2020-04-13 12:58:44 -06:00 |
|
tangxifan
|
07a384e440
|
now use openfpga tokenizer to trim command line string in openfpga shell
|
2020-04-13 11:08:31 -06:00 |