AurelienUoU
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c4ccff4562
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Move Verilog test in another script to avoid false failure
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2019-05-16 09:05:30 -06:00 |
AurelienUoU
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08f63c06c7
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Debug for Travis
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2019-05-15 16:55:18 -06:00 |
AurelienUoU
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57d75520a6
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Verilog verification with Travis
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2019-05-15 15:57:05 -06:00 |
tangxifan
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b04c6b8c31
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bug fix on Makefile and travis
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2019-05-03 23:24:08 -06:00 |
tangxifan
|
c5ef99f6d4
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update travis
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2019-05-03 23:18:31 -06:00 |
tangxifan
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e2e4a9287d
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keep bug fixing in Makefiles and remove parallism in Make
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2019-04-10 16:10:19 +08:00 |
tangxifan
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7c42119481
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Keep bug fixing for travis
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2019-04-10 16:00:03 +08:00 |
tangxifan
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5c46e4aabf
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add missing files for Travis
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2019-04-10 15:24:37 +08:00 |