Move Verilog test in another script to avoid false failure

.travis.yml

@@ -83,6 +83,7 @@ install:
 
 script:
   - .travis/script.sh
+  - .travis/regression.sh
 
 after_failure:
   - .travis/after_failure.sh

.travis/regression.sh

@@ -0,0 +1,40 @@
+#!/bin/bash
+# Regression test version 1.0
+
+# Set variables
+set benchmark = test_modes
+set include_netlists = _include_netlists.v
+set compiled_file = compiled_$benchmark
+set tb_formal_postfix = _top_formal_verification_random_tb
+set verilog_output_dirname = ${benchmark}_Verilog
+set log_file = ${benchmark}_sim.log
+
+# Move to vpr folder
+cd vpr7_x2p/vpr
+
+# Remove former log file
+rm $log_file
+rm $compiled_file
+
+# Start the script -> run the fpga generation -> run the simulation -> check the log file
+source .regression_verilog.sh
+iverilog -o $compiled_file $verilog_output_dirname/SRC/$benchmark$include_netlists -s $benchmark$tb_formal_postfix
+vvp $compiled_file -j 16 >> $log_file
+
+set result = `grep "Succeed" $log_file`
+if ("$result" != "")then
+  echo "Verification succeed"
+  cd -
+  exit 0
+else
+  set result = `grep "Failed" $log_file`
+  if ("$result" != "")then
+    echo "Verification failed"
+    cd -
+    exit 1
+  else
+    echo "Unexpected error, Verification didn't run"
+    cd -
+    exit 2
+  fi
+fi

.travis/script.sh

@@ -1,15 +1,5 @@
 #!/bin/bash
 
-# Set variables
-set benchmark = test_modes
-set include_netlists = _include_netlists.v
-set compiled_file = compiled_$benchmark
-set tb_formal_postfix = _top_formal_verification_random_tb
-set verilog_output_dirname = ${benchmark}_Verilog
-set log_file = ${benchmark}_sim.log
-
-$SPACER
-
 source .travis/common.sh
 set -e
 
@@ -33,41 +23,3 @@ fi
 end_section "OpenFPGA.build"
 
 $SPACER
-
-start_section "Verilog_test" "${GREEN}Testing..${NC}"
-# Begining of Verilog verification
-# Move to vpr folder
-cd vpr7_x2p/vpr
-echo "DEBUG_0"
-# Remove former log file
-rm $log_file
-rm $compiled_file
-echo "DEBUG_1"
-# Start the script -> run the fpga generation -> run the simulation -> check the log file
-source .regression_verilog.sh
-iverilog -o $compiled_file $verilog_output_dirname/SRC/$benchmark$include_netlists -s $benchmark$tb_formal_postfix
-echo "DEBUG_2"
-vvp $compiled_file -j 16 >> $log_file
-echo "DEBUG_3"
-set result = `grep "Succeed" $log_file`
-echo "DEBUG_4"
-if ("$result" != "")then
-  echo "Verification succeed"
-  cd -
-  exit 0
-else
-  set result = `grep "Failed" $log_file`
-  if ("$result" != "")then
-    echo "Verification failed"
-    cd -
-    exit 1
-  else
-    echo "Unexpected error, Verification didn't run"
-    cd -
-    exit 2
-  fi
-fi
-# End of Verilog verification
-end_section "Verilog_test"
-
-$SPACER